eZ80 CPU - writeframeofmind.biz

eZ80 CPU
User Manual
154
TST A, p, 140
TSTIO n, 141
XOR A, s, 142
instruction traps, illegal, 6
INT, 4
Interrupt Vector register, 2
interrupts, 4, 8
enabling and disabling, 4
locations, 6
maskable, 5
non-maskable, 5
vectored, 6
INTV, 4
IX register, 2
IY register, 2
J
JP (rr), 63
JP cc, Mmn, 65
JP Mmn, 64
JR cc, d, 67
JR d, 66
L
LCD A, I, 68
LD (HL), tt, 73
LD (ii), tt, 75
LD (Mmn), A, 77
LD (Mmn), qq, 78
LD (pp), A, 79
LD (uu), n, 88
LD (uu), r, 89
LD A, (Mmn), 70
LD A, (pp), 71
LD A, MB, 69
LD A, R, 72
LD I, A, 74
LD MB, A, 76
LD qq, Mmn, 80
LD r, (uu), 84
LD R, A, 81
LD r, n, 82
LD r, r’, 83
LD SP, rr, 85
LD tt,(HL), 86
LD tt,(ii), 87
LEA tt, IX+d, 91
LEA tt, IY+d, 90
legacy application guidelines, 12
M
MBASE, changing, 4
memory, 7
mixed ADL mode, 8
applications, 12
modes
ADL, 4
direct addressing mode, 8
immediate addressing mode, 7
indexed addressing mode, 8
modified page zero addressing mode, 7
native Z80, 3
register addressing mode, 8
register indirect addressing mode, 8
relative addressing mode, 8
switching between, 4
virtual Z80, 4
MUL ss, 92
N
N Flag (definition), 14
native Z80 mode, 3
NMI, 4
O
Op Code maps, 143
operating modes, 3
OR A, s, 93
OTD2R, 94
OTDM, 95
OTDMR, 96
OTDR, 97
UM007701-1100