eZ80 CPU - writeframeofmind.biz

eZ80 CPU
User Manual
75
Operation
Description
(ii) ← tt
LD (ii), tt
Load
The tt operand is any of BC, DE, HL, IX, or IY. The ii operand is any of IX+d or
IY+d. The contents of the multi-byte tt register, which remain unchanged, are
stored into the memory location specified by the contents of the multi-byte ii
register. The length of the multi-byte ii and tt registers may be a 16- or 24-bit
value, depending on the ADL mode. ADL mode may be overridden with the .S
or .L suffix.
Condition Bits Affected
Mnemonic Operands ADL Mode Cycles Op Codes
LD (IX+d),BC 0/1 5/6 DD, 0F, dd
LD.S (IX+d),BC 1 6 52, DD, 0F, dd
LD.L (IX+d),BC 0 7 49, DD, 0F, dd
LD (IX+d),DE 0/1 5/6 DD, 1F, dd
LD.S (IX+d),DE 1 6 52, DD, 1F, dd
LD.L (IX+d),DE 0 7 49, DD, 1F, dd
LD (IX+d),HL 0/1 5/6 DD, 2F, dd
LD.S (IX+d),HL 1 6 52, DD, 2F, dd
LD.L (IX+d),HL 0 7 49, DD, 2F, dd
LD (IX+d),IX 0/1 5/6 DD, 3F, dd
LD.S (IX+d),IX 1 6 52, DD, 3F, dd
LD.L (IX+d),IX 0 7 49, DD, 3F, dd
LD (IX+d),IY 0/1 5/6 DD, 3E, dd
LD.S (IX+d),IY 1 6 52, DD, 3E, dd
LD.L (IX+d),IY 0 7 49, DD, 3E, dd
LD (IY+d),BC 0/1 5/6 FD, 0F, dd
LD.S (IY+d),BC 1 6 52, FD, 0F, dd
LD.L (IY+d),BC 0 7 49, FD, 0F, dd
LD (IY+d),DE 0/1 5/6 FD, 1F, dd
LD.S (IY+d),DE 1 6 52, FD, 1F, dd
LD.L (IY+d),DE 0 7 49, FD, 1F, dd
LD (IY+d),HL 0/1 5/6 FD, 2F, dd
LD.S (IY+d),HL 1 6 52, FD, 2F, dd
LD.L (IY+d),HL 0 7 49, FD, 2F, dd
LD (IY+d),IX 0/1 5/6 FD, 3E, dd
LD.S (IY+d),IX 1 6 52, FD, 3E, dd
LD.L (IY+d),IX 0 7 49, FD, 3E, dd
LD (IY+d),IY 0/1 5/6 FD, 3F, dd
LD.S (IY+d),IY 1 6 52, FD, 3F, dd
LD.L (IY+d),IY 0 7 49, FD, 3F, dd
UM007701-1100