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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
21<br />
ADD rr, ss<br />
ADD without Carry<br />
Operation<br />
Description<br />
rr ← rr + ss<br />
The ss operand is any of the BC, DE, HL, or SP registers. The destination rr<br />
register is any of the HL, IX, or IY registers. The ss operand is added to the<br />
contents of the rr register, which contain the result. ADL mode affects<br />
operations with the HL, IX, IY, BC, DE, and SP registers. ADL mode may be<br />
overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
Not affected.<br />
Not affected.<br />
Set if carry from Bit 11; reset otherwise.<br />
Not affected.<br />
Reset.<br />
Set if carry from MSB; reset otherwise.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
ADD HL,ss X 1 kk<br />
ADD.S HL,ss 1 2 52, kk<br />
ADD.L HL,ss 0 2 49, kk<br />
ADD IX,ss X 2 DD, kk<br />
ADD.S IX,ss 1 3 52, DD, kk<br />
ADD.L IX,ss 0 3 49, DD, kk<br />
ADD IY,ss X 2 FD, kk<br />
ADD.S IY,ss 1 3 52, FD, kk<br />
ADD.L IY,ss 0 3 49, FD, kk<br />
kk = binary code 00 ss1 001 where ss identifies the BC, DE, HL, or SP register<br />
assembled as follows into the object code.<br />
Register<br />
ss<br />
BC 00<br />
DE 01<br />
HL 10<br />
SP 11<br />
UM007701-1100
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