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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
80<br />
LD qq, Mmn<br />
Load<br />
Operation<br />
Description<br />
qq ← Mmn<br />
The qq operand is any of BC, DE, HL, SP, IX, or IY. The immediate Mmn<br />
operand is loaded into the multi-byte qq register. The SP register is special in<br />
that SPL is used in ADL mode and SPS is used in non-ADL mode.<br />
ADL mode affects operations with the BC, DE, HL, SP, IX, or IY register . ADL<br />
mode may be overridden with the .SIS or .LIL suffix.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
LD ss,mn 0 3 kk, nn, mm<br />
LD ss,Mmn 1 4 kk, nn, mm, MM<br />
LD.LIL ss,Mmn 0 5 5B, kk, nn, mm, MM<br />
LD.SIS ss,mn 1 4 40, kk, nn, mm<br />
LD IX,mn 0 4 DD, 21, nn, mm<br />
LD IX,Mmn 1 5 DD, 21, nn, mm, MM<br />
LD.LIL IX,Mmn 0 6 5B, DD, 21, nn, mm, MM<br />
LD.SIS IX,mn 1 5 40, DD, 21, nn, mm<br />
LD IY,mn 0 4 FD, 21, nn, mm<br />
LD IY,Mmn 1 5 FD, 21, nn, mm, MM<br />
LD.LIL IY,Mmn 0 6 5B, FD, 21, nn, mm, MM<br />
LD.SIS IY,mn 1 5 40, FD, 21, nn, mm<br />
kk = binary code 00 ss0 001 where ss identifies the BC, DE, HL, or SP register<br />
assembled as follows in the object code:<br />
Register<br />
ss<br />
BC 00<br />
DE 01<br />
HL 10<br />
SP 11<br />
UM007701-1100
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