eZ80 CPU - writeframeofmind.biz

eZ80 CPU
User Manual
142
XOR A, s
Logical Exclusive-OR
Operation
Description
A ← A ⊕ s
The s operand is any of r, n, (HL), (IX+d), or (IY+d). The s operand is bitwise
exclusive-OR’ed with the contents of the Accumulator, which contains the
result. ADL mode affects operations with the HL, IX, and IY registers. ADL
mode may be overridden with the .S or .L suffix.
Condition Bits Affected
S
Z
H
P/V
N
C
Set if result is negative; reset otherwise.
Set if result is zero; reset otherwise.
Set.
Set if parity is even; reset otherwise.
Reset.
Reset.
Mnemonic Operands ADL Mode Cycles Op Codes
XOR A,r X 1 jj
XOR A,n X 2 EE, nn
XOR A,(HL) X 2 AE
XOR.S A,(HL) 1 3 52, AE
XOR.L A,(HL) 0 3 49, AE
XOR A,(IX+d) X 4 DD, AE, dd
XOR.S A,(IX+d) 1 5 52, DD, AE, dd
XOR.L A,(IX+d) 0 5 49, DD, AE, dd
XOR A,(IY+d) X 4 FD, AE, dd
XOR.S A,(IY+d) 1 5 52, FD, AE, dd
XOR.L A,(IY+d) 0 5 49, FD, AE, dd
jj = binary code 10 101 rrr where rrr identifies the A, B, C, D, E, H, or L
register assembled as follows into the object code:
Register rrr
A 111
B 000
C 001
D 010
E 011
H 100
L 101
UM007701-1100