Create successful ePaper yourself
Turn your PDF publications into a flip-book with our unique Google optimized e-Paper software.
<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
50<br />
INC m<br />
Increment<br />
Operation<br />
Description<br />
m ← m + 1<br />
The m operand is any of r, (HL), (IX+d), or (IY+d). The m operand increments by<br />
1. ADL mode affects operation with the HL, IX, and IY registers. ADL mode may<br />
be overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
S Set if result is negative; reset otherwise.<br />
Z Set if result is zero; reset otherwise.<br />
H Set if carry from Bit 3.<br />
P/V Set if operand was 7FH before operation.<br />
N Reset.<br />
C Not affected.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
INC r X 1 jj<br />
INC (HL) X 4 34<br />
INC.S (HL) 1 5 52, 34<br />
INC.L (HL) 0 5 49, 34<br />
INC (IX+d) X 6 DD, 34, dd<br />
INC.S (IX+d) 1 7 52, DD, 34, dd<br />
INC.L (IX+d) 0 7 49, DD, 34, dd<br />
INC (IY+d) X 6 FD, 34, dd<br />
INC.S (IY+d) 1 7 52, FD, 34, dd<br />
INC.L (IY+d) 0 7 49, FD, 34, dd<br />
jj = binary code 00 rrr 100 where rrr identifies the A, B, C, D, E, H, or L<br />
register assembled as follows into the object code.<br />
Register<br />
rrr<br />
A 111<br />
B 000<br />
C 001<br />
D 010<br />
E 011<br />
H 100<br />
L 101<br />
UM007701-1100
Change language