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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
110<br />
PEA IY+d<br />
Push Effective Address<br />
Operation<br />
Description<br />
if .L or (ADL and not .S)<br />
SPL ← SPL – 3<br />
(SPL) ← IY+d<br />
else<br />
SPS ← SPS – 2<br />
(SPS) ← IY+d<br />
In ADL mode, SPL decrements by three and the 24-bit sum of the contents of IY<br />
and the signed displacement d is pushed onto the stack at SPL. In non-ADL<br />
mode, SPS decrements by two and the 16-bit sum of the contents of IY and the<br />
signed displacement d is pushed onto the stack at SPS.<br />
ADL mode affects operations with the IY or SP register. ADL mode may be<br />
overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
PEA IY+d 0/1 5/6 ED, 66, dd<br />
PEA.S IY+d 1 6 52, ED, 66, dd<br />
PEA.L IY+d 0 7 49, ED, 66, dd<br />
UM007701-1100
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