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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
49<br />
INC qq<br />
Increment Register<br />
Operation<br />
Description<br />
If .L or (ADL and not .S)<br />
qq[23:0] ← qq[23:0] + 1<br />
else<br />
qq[15:0] ← qq[15:0] + 1<br />
qq[23:16] ← 0<br />
The qq operand is any of the BC, DE, HL, SP, IX, or IY registers. The contents<br />
of the specified register increment by 1. ADL mode affects operation with the<br />
BC, DE, HL, SP, IX and IY registers. ADL mode may be overridden with the .S<br />
or .L suffix.<br />
Condition Bits Affected<br />
None<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
INC ss X 1 kk<br />
INC.S ss 1 2 52, kk<br />
INC.L ss 0 2 49, kk<br />
INC IX X 1 DD, 23<br />
INC.S IX 1 2 52, DD, 23<br />
INC.L IX 0 2 49, DD, 23<br />
INC IY X 1 FD, 23<br />
INC.S IY 1 2 52, FD, 23<br />
INC.L IY 0 2 49, FD, 23<br />
kk = binary code 00 ss0 011 where ss identifies the BC, DE, HL, or SP register<br />
assembled as follows into the object code.<br />
Register<br />
ss<br />
BC 00<br />
DE 01<br />
HL 10<br />
SP 11<br />
UM007701-1100
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