eZ80 CPU - writeframeofmind.biz

eZ80 CPU
User Manual
24
CALL Mmn
CALL Subroutine
Operation
Description
(SP) ← PC
PC ← Mmn
The return address, which follows this instruction, is pushed onto the stack and
then the program counter is loaded with the Mmn operand and execution
continues at that address. The Mmn operand is a 16- or 24-bit address,
depending on the instruction and/or the ADL mode. The low-order byte of the
mn operand is the first byte after the Op Code.
ADL Prefix Operation
0 None Stack 2-byte logical return address using SPS mapped by MBASE.
Keep ADL cleared to 0. Load a 2-byte logical address from the instruction into PC.
1 None Stack 3-byte return address using SPL.
Keep ADL set to 1. Load a 3-byte logical address from the instruction into PC.
0 .IS Stack 2-byte logical return address using SPS mapped by MBASE.
Stack a 00 byte using SPL.
Keep ADL cleared to 0. Load a 2-byte logical address from the instruction into PC.
1 .IS Stack 2 LS bytes of the return address using SPS mapped by MBASE.
Stack the MS byte of the return address using SPL.
Stack a 01 byte using SPL.
Clear ADL to 0. Load a 2-byte logical address from the instruction into PC.
0 .IL Stack 2-byte logical return address using SPL.
Stack a 00 byte using SPL.
Set ADL to 1. Load a 3-byte address from the instruction into PC.
1 .IL Stack 3-byte return address using SPL.
Stack a 01 byte using SPL.
Keep ADL set to 1. Load a 3-byte address from the instruction into PC.
Condition Bits Affected
None
Mnemonic Operands ADL Mode Cycles Op Codes
CALL mn 0 5 CD, mn, mn
CALL Mmn 1 7 CD, mn, mn, MM
CALL.IS mn 0 7 40, CD, mn, mn
CALL.IS mn 1 8 49, CD, mn, mn
CALL.IL Mmn 0 8 52, CD, mn, mn, MM
CALL.IL Mmn 1 9 5B, CD, mn, mn, MM
UM007701-1100