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<strong>eZ80</strong> <strong>CPU</strong><br />
User Manual<br />
30<br />
CPDR<br />
Compare Decrement Repeat<br />
Operation<br />
Description<br />
repeat :<br />
{ A – (HL)<br />
HL ← HL – 1<br />
BC ← BC – 1<br />
} while (not Z and BC ≠ 0)<br />
The contents of the memory location that the HL register points to are compared<br />
to the contents of the Accumulator, which are not affected by this instruction.<br />
The HL and BC registers are decremented. The above operation is repeated,<br />
unless<br />
A = (HL) or BC are decremented to zero.<br />
ADL mode affects operation with the HL and BC registers. ADL mode may be<br />
overridden with the .S or .L suffix.<br />
Condition Bits Affected<br />
S<br />
Z<br />
H<br />
P/V<br />
N<br />
C<br />
Set if result is negative; reset otherwise.<br />
Set if A = (HL); reset otherwise.<br />
Set if borrow from Bit 4; reset otherwise.<br />
Set if BC –1 ≠ 0; reset otherwise.<br />
Set.<br />
Not affected.<br />
Mnemonic Operands ADL Mode Cycles Op Codes<br />
CPDR — X 4/3 ED, B9<br />
CPDR.S — 1 5/3 52, ED, B9<br />
CPDR.L — 0 5/3 49, ED, B9<br />
UM007701-1100
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