Soft-Core Processor Design - CiteSeer

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� ��¥ � �� ¢¤£¦¥ ¢¤£¦¥ ¢¤£¦¥ ¢¤£¦¥ ¢¤£¦¥ ¢¤£¦¥ ¢¤£¦¥ ¢¤£¦¥ Each logic block can implement only small functions of several variables. Programmable interconnection, also called routing, is used to connect logic blocks into larger circuits performing the required functionality. Routing consists of wires that span one or more logic blocks. Connections between logic blocks and routing, I/O blocks and routing, and among wires themselves is programmable, which allows for the flexibility of circuit implementation. Routing is a very important aspect of FPGA devices, because it dominates the chip area and most of the circuit delay is due to the routing delays [11]. �� I/O blocks in an FPGA connect the internal logic to the outside pins. Depending on an actual device, most pins can be configured as either input, output, or bidirectional. Devices supporting more than one I/O standard allow configuration of different pins for different standards [12]. Programmability of FPGAs is commonly achieved using one of three technologies: SRAM cells, antifuses, and floating gate devices. Most devices use SRAM cells. The SRAM cells drive pass transistors, multiplexers, and tri-state buffers, which in turn control the configurable routing, 6 �� Figure 2.1 Simple logic block structure ¡ �� §©¨��
logic and I/O blocks [11]. Since the content of SRAM cells is lost when the device is not powered, the configuration needs to be reloaded into the device on each power-up. This is done using a configuration device that loads the configuration stored in some form of non-volatile memory. Programmability of FPGAs comes at a price. Resources necessary for the programmability take up chip area and consume power. Therefore, circuits implemented in FPGAs take up more area and consume more power than in equivalent ASIC implementations. Furthermore, since the routing in FPGAs is achieved using programmable switches, as opposed to metal wires in ASICs, circuit delays in FPGAs are higher. Because of that, care has to be taken to exploit the resources in an FPGA efficiently. Circuit speed is important for high-throughput applications like Digital Signal Processing (DSP), while power is important for embedded applications. CAD tools are used by the designer to meet these requirements. 2.3. FPGA <strong>Design</strong> Flow <strong>Design</strong>ing a complex system targeting FPGAs would be virtually impossible without CAD tools. The CAD tools convert the user’s specification into an FPGA configuration that implements the specified functionality, while optimizing one or more design parameters. Common optimizations include reducing the chip area, increasing the speed, and reducing the power usage. The CAD tools perform a set of steps to map the design specification to an FPGA. Figure 2.2 shows the design flow of typical CAD tools targeting FPGAs [11]. Input to a CAD tool is a high-level circuit description, which is typically provided using a hardware description language (HDL). VHDL (Very High Speed Integrated Circuit Hardware Description Language) and Verilog HDL are the two most popular HDLs in use today. An HDL circuit description is converted into a netlist of basic gates in the synthesis step of the design flow. The netlist is optimized using technology-independent logic minimization algorithms. The optimized netlist is mapped to the target device using a technology-mapping algorithm. A minimization algorithm ensures that the circuit uses as few logic blocks as possible. Further optimizations that exploit the structure of the underlying FPGA are also performed. For instance, some FPGAs group logic blocks in clusters, with high connectivity among the blocks inside the cluster, and less routing resources connecting logic blocks in different clusters. This is usually referred to as hierarchical routing. The synthesis tool will use information on the cluster size and connectivity to map logic that requires many connections inside a cluster. This optimization is 7
Page 1 and 2: SOFT-CORE PROCESSOR DESIGN by Franj
Page 3 and 4: Acknowledgments First, I would like
Page 5 and 6: 5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11: uilt using techniques proven to be
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64:
underflow and overflow exceptions a
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Slowdown Over 29 Available Register
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Recursion Level # of recursive call
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Total # of Memory Accesses Performe
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System SRAM ONCHIP Size of the Regi
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a fixed access time, since it is no
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Speedup of the Pipeline Optimized f
Page 77 and 78:
Improvement of UT Nios over Altera
Page 79 and 80:
Improvement of UT Nios over Altera
Page 81 and 82:
Number of Processors LEs (% increas
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pipelined implementation. Control-f
Page 85 and 86:
not mean that, for example, the ins
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There are many paths in each group,
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FPGA design flow is a random functi
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each be connected to only a single
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• The UT Nios design is analyzed
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[13] C. Blum and A. Roli, “Metahe
Page 97 and 98:
[36] Microchip Technology, “PIC16
Page 99:
[60] Altera Corporation, “AN 184:
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