Soft-Core Processor Design - CiteSeer

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[48] Altera Corporation, “GNUPro - User's Guide for Altera Nios,” [Online Document], 2000 June, [Cited 2004 February 20], Available HTTP: http://www.altera.com/literature/third-party/nios_gnupro.pdf [49] Red Hat, Inc., “GNUPro Developer Tools,” [Online Document, Cited 2004 February 20], Available HTTP: http://www.redhat.com/software/gnupro [50] Altera Corporation, “Nios Development Kit, Stratix Edition,” [Online Document, Cited 2004 March 2], Available HTTP: http://www.altera.com/products/devkits/altera/kit-nios_1S10.html [51] Altera Corporation, “Nios Development Kit, Cyclone Edition,” [Online Document, Cited 2004 March 3], Available HTTP: http://www.altera.com/products/devkits/altera/kit-nios_1C20.html [52] Altera Corporation, “Nios Development Kit,” [Online Document, Cited 2004 March 3], Available HTTP: http://www.altera.com/products/devkits/altera/kit-nios.html [53] Altera Corporation, “APEX 20K Device Family Architecture,” [Online Document, Cited 2004 March 4], Available HTTP: http://www.altera.com/products/devices/apex/features/apx-architecture.html#esb [54] Altera Corporation, “Single & Dual-Clock FIFO Megafunctions User Guide,” [Online Document], 2003 June, [Cited 2004 March 4], Available HTTP: http://www.altera.com/literature/ug/ug_fifo.pdf [55] S. Subramanian, A Methodology For Mapping Networking Applications To Multiprocessor-FPGA Configurable Computing Systems, Ph.D. Thesis, North Carolina State University, Raleigh, NC, 2003. [56] M. R. Guthaus and J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, R. B. Brown, “MiBench: A Free, Commercially Representative Embedded Benchmark Suite,” In Proc. of the 4 th IEEE Workshop on Workload Characterization, Austin, TX, 2001, pp. 3-14. [57] L. Shannon and P. Chow, “Standardizing the Performance Assessment of Reconfigurable Processor Architectures,” [Online Document, Cited 2004 March 11], Available HTTP: http://www.eecg.toronto.edu/~lesley/benchmarks/rates/shannon_rates.ps [58] Altera Corporation, “ByteBlasterMV Parallel Port Download Cable,” [Online Document], 2002 July, [Cited 2004 March 11], Available HTTP: http://www.altera.com/literature/ds/dsbytemv.pdf [59] Altera Corporation, “Nios Development Board Reference Manual, Stratix Edition,” [Online Document], 2003 July, [Cited 2004 March 11], Available HTTP: http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf 92
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Page 1 and 2:
SOFT-CORE PROCESSOR DESIGN by Franj
Page 3 and 4:
Acknowledgments First, I would like
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5.1.2. Development Tools ..........
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Chapter 1 Introduction Since their
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Chapter 2 Background Soft-core proc
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uilt using techniques proven to be
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logic and I/O blocks [11]. Since th
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timing-driven [11]. Although simula
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the HDL coding style. To ensure tha
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3.1. Nios Architecture The Nios ins
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esult of a read operation from thes
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satisfied the instruction that foll
Page 25 and 26:
Most instructions take 5 cycles to
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contents of the register window wil
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needed, the master asserts the flus
Page 31 and 32:
There are several ways in which use
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code) is provided [47]. Both printf
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memory address has to be set in the
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parameters include the general-purp
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Similarly, the control-flow instruc
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the logic resources may be more cri
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simple dual-port mode, which means
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prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
Page 83 and 84: pipelined implementation. Control-f
Page 85 and 86: not mean that, for example, the ins
Page 87 and 88: There are many paths in each group,
Page 89 and 90: FPGA design flow is a random functi
Page 91 and 92: each be connected to only a single
Page 93 and 94: • The UT Nios design is analyzed
Page 95 and 96: [13] C. Blum and A. Roli, “Metahe
Page 97: [36] Microchip Technology, “PIC16
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