Soft-Core Processor Design - CiteSeer

esult of a read operation from these registers is undefined. Other control registers include CPU
ID (%ctl6) which identifies the version of the Altera Nios processor, and several reserved
registers whose function is not defined in the documentation [22,23]. The 32-bit Altera Nios also
has control registers ICACHE (%ctl5) and DCACHE (%ctl7), used to invalidate cache lines in
the instruction and data caches, respectively. Both ICACHE and DCACHE are write-only
registers. Reading these registers produces an undefined value.
Control registers can be directly read and written to by using instructions RDCTL and
WRCTL, respectively. Control registers can also be modified implicitly as a result of other
operations. Condition code flags are updated by arithmetic and logic instructions depending on
the result of their operation. Fields IPRI and IE bit in the STATUS register are modified, and the
old value of the STATUS is stored to the ISTATUS register when the interrupt occurs.
The register set also includes the program counter (PC) and the K register. The program
counter holds the address of the instruction that is being executed. K is an 11-bit register used to
form longer immediate operands. Since both 16- and 32-bit Nios have an instruction word that is
16-bits wide, it is not possible to fit a 16-bit immediate operand into the instruction word. The
16-bit immediate value is formed by concatenating the 11-bit value in the K register with the 5-bit
immediate operand from the instruction word. The K register is set to 0 by any instruction other
than PFX, which is used to load the K register with the 11-bit immediate value specified in the
instruction word. The PFX instruction and the instruction following it are executed atomically.
Interrupts are disabled until the instruction following the PFX commits. The PFXIO instruction is
available only in the 32-bit Altera Nios; it behaves just like the PFX instruction except that it
forces the subsequent memory load operation to bypass the data cache.
3.1.2. Nios Instruction Set
The Nios instruction set is optimized for embedded applications [33]. To reduce the code size,
all instruction words are 16-bits wide in both 16- and 32-bit Nios architectures. Previous research
on other architectures has shown that using the 16-bit instruction width can produce up to 40%
reduction in code size compared to the 32-bits wide instruction word [34]. Nios is a load-store
architecture with the two-operand instruction format and 32 addressable general-purpose
registers. More than ten different instruction formats exist to accommodate the addressing modes
available.
The Nios instruction set supports several addressing modes, including 5/16-bit immediate,
register, register indirect, register indirect with offset, and relative mode. Many arithmetic and
logic instructions use 5-bit immediate operands specified in the instruction word. If such an
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