Soft-Core Processor Design - CiteSeer

timing-driven [11]. Although simulated annealing produces suboptimal results, a good choice of
the cost function yields average results that are reasonably close to optimal.
Once the placement has been done, the routing algorithm determines how to interconnect the
logic blocks using the available routing. The routing algorithm can also be timing- or
routability-driven. While a routability-driven algorithm only tries to allocate routing resources so
that all signals can be routed, a timing-driven algorithm tries also to minimize the routing delays
[15]. The routing algorithm produces a set of programming bits determining the state of all the
interconnection switches inside an FPGA.
The final output the CAD tools produce is the FPGA programming file, which is a bit stream
determining the state of every programmable element inside an FPGA. Design flow, including
synthesis, placement and routing is sometimes referred to as the design compilation. Although the
term synthesis is also commonly used, we will use the term design compilation to avoid
confusion between the synthesis step of the design flow, and the complete design flow.
Although design compilation does not generally require the designer’s assistance, modern
tools allow the designer to direct the synthesis process by specifying various parameters. Even
variations in the initial specification can influence the quality of the final result (examples of such
behaviour will be shown later in the thesis). This suggests that the designer should understand the
CAD tools and the underlying technology to fully exploit the capabilities of both tools and the
device. In the following section we give an overview of the CAD tool and the FPGA device used
in the thesis.
2.4. Stratix FPGA and Quartus II CAD Tool
The previous two sections presented a general FPGA architecture and CAD design flow. In
this section, the Stratix FPGA device family [12] used for the implementation of UT Nios is
presented. The CAD tool Quartus II [16], used for the synthesis of the UT Nios design, is also
described.
The terminology used in Stratix documentation [12] is somewhat different than that presented
in section 2.1. A logic element (LE) is very similar to the logic block depicted in Figure 2.1. It
consists of a 4-LUT, a register (flip-flop), a multiplexer to choose between the LUT and the
register output, and additional logic required for advanced routing employed in Stratix. Special
kinds of interconnection; LUT chains, register chains, and carry chains, are used to minimize the
routing delay and increase capabilities of groups of LEs. Groups of 10 LEs are packed inside
clusters called Logic Array Blocks (LABs), with a hierarchical routing structure [12].
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