Soft-Core Processor Design - CiteSeer

FPGA design flow is a random function of the circuit design and a seed. “A seed is a parameter
that affects the random initial placement of the Quartus II fitter” [16]. The Quartus II
documentation suggests that the seed value has small influence on the final compilation result
[16]. However, our experiments show that the seed may have a large impact on the compilation
results. We analyzed the compilation results of the UT Nios based system using 20 different
seeds, and found that the results varied as much as 14.9%. Furthermore, exploring how the
compilation results of seven different systems vary with different seeds, we found that on
average, the difference between the best and the worst case over 20 seeds was 12.4%. But, the
difference between the best and the average case was only 5.6% in this experiment. Therefore, we
believe that the designers should always do a seed sweep as part of the recommended design
process. The seed value does not influence the number of LEs required for the design
implementation; it influences only how the LEs are placed inside the device.
The compilation result variations affected the methodology used in this work. We based our
design decisions on the results from the timing analysis provided by Quartus II. Since the initial
placement changes whenever the netlist changes, we compiled each design with multiple seeds,
and based the decisions on the maximum Fmax values obtained. The fluctuations in the Fmax have
another implication on the design process that we have observed. Since the development board
contains only a 50 MHz clock signal, we have used PLLs to synthesize the appropriate clock
speed for the system. The system has to be compiled once before introducing the PLL to
determine the Fmax. However, when the PLL that produces the clock signal with the obtained Fmax
is introduced in the design, the new compilation result often does not achieve the previously
obtained Fmax. Therefore, the design has to be compiled several times again, with different seeds,
until the seed that produces the original Fmax is found. Another option is to use the Quartus II
LogicLock feature. The feature enables users to lock the placement and routing of the circuit, or
part of the circuit, so the performance of that circuit remains constant when other modules are
added to the design and the design is recompiled.
The nature of state machine processing is another synthesis parameter available in Quartus II
that may have a significant impact on the performance of some designs. The state machine
processing defines how the states in a state machine are encoded. The available options are:
minimal bits, one-hot, user-encoded, and auto (compiler selected). The state machines in the
Verilog design files are automatically recognized if the state machine specification follows the
guidelines outlined in [16]. The value of the state machine processing parameter has very little
effect on our current design (less than 1%). However, at one point during the design process, the
control unit state machine had 14 states. Encoding the states using one-hot encoding in that case
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