Soft-Core Processor Design - CiteSeer

In addition to optional instructions, the Altera Nios instruction set can be customized by
defining up to five user-defined (custom) instructions. Instruction encoding reserves five OP
codes for user instructions. In the assembly language, user instructions can be referred to using
mnemonics USR0 through USR4. User instruction functionality is defined as a module with a
predefined interface [24]. Functionality specification can be given using any of the design entry
formats supported by Quartus II. Both single-cycle (combinational), and multi-cycle (sequential)
operations are allowed in user instructions. The number of cycles it takes for a multi-cycle
operation to produce the result has to be fixed and declared at the system design time. Custom
instruction logic is added in parallel to the functional units of the Nios processor, which
corresponds to a closely coupled reconfigurable system. A module with user instruction
specification can also interface user logic external to the processor, as shown in Figure 3.2 [24].
3.1.3. Datapath and Memory Organization
The Altera Nios datapath is organized as a 5-stage single-issue pipeline with separate data and
instruction masters. The data master performs memory load and store operations, while the
instruction master fetches the instructions from the instruction memory. Many pipeline details are
not provided in the Altera literature.
Figure 3.2 Adding custom instructions to Nios [24]
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