Soft-Core Processor Design - CiteSeer

There are many paths in each group, because the Quartus II Timing Analyzer does not group
the bits corresponding to a bus or a register, but reports each path individually. It is interesting
that the groups of the analyzed paths are scattered throughout the datapath. This suggests that the
delays in the design are well balanced, and that major performance improvements cannot be
achieved by changing a single part of the design. In fact, even if the 200 most critical paths were
removed, the Fmax would only increase to 81.5 MHz (from 79 MHz) for the SRAM system.
Furthermore, if the 10,000 most critical paths were removed, the Fmax would increase to 87.6
MHz. Although the number of actual paths in the design corresponding to the 10,000 paths
reported by the Timing Analyzer is much lower (because the results are expressed in bit
granularity), it is obvious that major design changes have to be made to obtain a significant
performance improvement.
Comparing the UT Nios design to the Altera Nios reveals an interesting trade-off between the
Fmax and the cycle count, the two parameters that define the processor performance. The UT Nios
design process was guided by the assumption that pipeline stalls should be minimized. The initial
design with only two pipeline stages was perfect in this regard, because it had the best CPI
theoretically possible. However, since the performance was not satisfactory, the condition to
minimize the pipeline stalls was relaxed until better performance was achieved. On the other
hand, the Altera Nios implementation is optimized for high Fmax, while sacrificing the cycle
count. Having in mind that both implementations achieve similar performance, it is not obvious
which approach is better. Higher Fmax is better from the marketing perspective. The UT Nios has
approximately 30% lower Fmax than the Altera Nios (Table 5.3), which may result in lower power
consumption. However, since the UT Nios based system uses approximately 20% more logic
(Table 5.4), its power consumption would be only 16% lower than that of the Altera Nios,
assuming that the power consumption grows linearly with the Fmax and the area used.
Another interesting result of the timing analysis of the UT Nios implementation is that none of
the most critical paths includes a shifter ALU unit, even though the shift operations are performed
within a single cycle, while the Altera Nios takes two cycles to perform the shift operation. This
could be because either the Altera Nios implements the shifter unit poorly, or the shift operations
become more critical when the number of pipeline stages increases.
As suggested in the previous chapter, having a smaller general-purpose register file may open
new opportunities for the organization of the pipeline. For example, in traditional pipeline
organizations [34], the operand reading is performed in parallel with instruction decoding. This is
not possible with the current UT Nios implementation, because of the variety of addressing
modes supported by the Nios architecture. Therefore, the instruction has to be decoded first to
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