Soft-Core Processor Design - CiteSeer

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Figure 3.3 Hardware and software design flow for a Nios processor system [44] 3.3.1. SOPC Builder SOPC Builder [45] is a tool for the integration and configuration of a bus-based system consisting of library and user components. Library components include processors, memories, bus arbiters and bridges, standard peripherals, and other IP cores. Each component is described in a class.ptf peripheral template file (PTF). The class.ptf file is a text file containing all the information necessary to integrate the component in the system. Library components are usually provided as a synthesizable HDL description (although other formats supported by Quartus II may also be used), or the component generator program. The generator program usually emits synthesizable HDL based on the user options, thus enabling high core flexibility. Library components that need to be accessed by software provide software libraries and drivers. 24
There are several ways in which user components can be added to the system. Some user components provide their own class.ptf file. If a user component is used in many designs, a class.ptf file makes the reuse of the component easier because it can be added to the system in the same way as any library component. To connect a user component without a class.ptf file to the system, it is necessary to define the mapping of component ports to Avalon bus signals. However, if the user component resides off-chip, or its design is not available at the time the system is created, an interface to user logic can be defined. The interface to user logic is a subset of the Avalon bus signals used by the user component external to the system generated by the SOPC builder. The SOPC Builder consists of two parts: graphical user interface (GUI), and a system generator program. The GUI is used to select system components, and to set various component and system parameters. Each component provides its own set of parameters that can be customized. For instance, the Altera Nios processor provides a set of configurable options, as described in section 3.1. Depending on the peripheral type, memory mapping and the interrupt priority may be defined. System components are automatically interconnected using one of the available buses. The SOPC Builder supports two bus types: AMBA–AHB [46] and Avalon [25]. Each component defines the type of bus used to connect it to the rest of the system. If the system includes components designed for different buses that need to be interconnected, a bridge component is used to translate signals and protocols between the different types of buses. Various system parameters can be defined using the SOPC Builder GUI. Interconnections between masters and slaves are defined according to the system requirements. If more than one master connects to a slave, the arbitration priorities can be defined, or the default values are used. System clock frequency has to be specified at design time, since some system components may require precise clock information (e.g. the UART uses the clock to generate the baud rate). Some component generator programs can emit the HDL code specialized for various FPGA device families. Therefore, the FPGA device family that will be used for the system implementation has to be specified. Various software settings, like the program starting address, vector table memory location, and library settings also have to be defined. If the system includes on-chip memory, the initial memory contents used in both synthesis and simulation can be specified. For off-chip memory, only the simulation contents can be specified, because the contents of the off-chip memory are not a part of the FPGA programming file. The system configuration defined in the SOPC Builder GUI is stored in a system PTF file, which is a plain text file that completely describes the system. The system generator program uses the information in the system PTF file to generate HDL code and software for the system. It first 25
Page 1 and 2: SOFT-CORE PROCESSOR DESIGN by Franj
Page 3 and 4: Acknowledgments First, I would like
Page 5 and 6: 5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11 and 12: uilt using techniques proven to be
Page 13 and 14: logic and I/O blocks [11]. Since th
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29: needed, the master asserts the flus
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82:
Number of Processors LEs (% increas
Page 83 and 84:
pipelined implementation. Control-f
Page 85 and 86:
not mean that, for example, the ins
Page 87 and 88:
There are many paths in each group,
Page 89 and 90:
FPGA design flow is a random functi
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each be connected to only a single
Page 93 and 94:
• The UT Nios design is analyzed
Page 95 and 96:
[13] C. Blum and A. Roli, “Metahe
Page 97 and 98:
[36] Microchip Technology, “PIC16
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[60] Altera Corporation, “AN 184:
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