Soft-Core Processor Design - CiteSeer

Total # of Memory Accesses Performed by the CWP Manager
8000
7000
6000
5000
4000
3000
2000
1000
0
1 2 3 4 5 6 7 8 9 10 11 12
Number of Register Windows Available to the Program
Figure 5.7 Modelled number of memory accesses vs. the number of the available register
windows for the Fibo benchmark
number of the available register windows increases from 4 to 5. This is further augmented by the
increasing number of memory operations per exception, as shown in Table 5.1.
Comparing the results in Figure 5.7 to the results for Fibo in Figure 5.5 shows that the total
number of memory operations caused by the register window exceptions is a good indicator of
performance of the Fibo benchmark on the SRAM system. The results are slightly different on the
ONCHIP system (Figure 5.4), which is expected because the memory latency is lower, so the
memory operations have less impact on the overall performance.
To verify the proposed model, we calculated the number of memory operations performed by
a simple procedure that performs only a single recursive call at each recursion level (except the
last level). The Recursive bit count by nibbles algorithm from the Bitcount benchmark is an
example of such program. It performs 8 recursive calls to count the number of bits in the 32-bit
input data, and therefore causes from 8 to 0 register window exceptions as the number of the
available register windows grows from 1 to 9. More precisely, the number of register window
exceptions is 8, 4, 2, 2, 1, 1, 1, 1, 0. Multiplying these numbers by the number of the memory
operations per register window exception yields the values shown graphically in Figure 5.8.
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