Soft-Core Processor Design - CiteSeer

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The FSM could be simplified by unifying the LOAD and STORE states into a single state, since their behaviour with respect to the inputs is identical and they differ in only 3 output signals. However, simplifying the FSM in such a way does not improve performance or reduce the amount of logic resources used by the FSM, while in some system configurations it even hurts the performance. The performance of UT Nios is investigated in the next chapter. 46
Chapter 5 Performance This chapter investigates the performance of the UT Nios implementation described in the previous chapter. First, the methodology used to measure the performance is described. Next, the effects of various architectural parameters on performance are investigated. Finally, a performance comparison of the UT Nios and 32-bit Altera Nios is presented. Although the emphasis is on the performance, the FPGA area requirements are also taken into consideration. 5.1. Methodology 5.1.1. UT Nios Benchmark Set To assess the performance of a computer architecture, a set of benchmark programs has to be defined. The benchmark set should be representative of the programs that are commonly run on the architecture. Hence, to define a good benchmark set, it is necessary to determine the characteristics of programs that are used in Nios-based systems. We refer to the benchmark set defined in this chapter as the UT Nios benchmark set. The Nios architecture is intended for use in FPGA-based systems. FPGAs are typically built into systems for two reasons: speeding up the performance of critical parts of an application, and system reconfigurability. Performance critical parts of the application are implemented in logic because such implementation does not incur overheads associated with the instruction fetching and decoding in a software implementation. For instance, DSP functions can be implemented efficiently in the DSP blocks of Stratix FPGA chips, while an equivalent implementation in software running on a general-purpose microprocessor incurs the overheads that limit the performance. Auxiliary functions, performing simple operations, are more likely to be implemented in software using a general-purpose microprocessor like Nios. They include functions such as simple data conversions or header processing in network applications. Using a soft-core processor, instead of mapping the whole application into hardware, results in better logic utilization [55]. Performance is still an issue, because the soft-core processor has to be able to handle the data at the same rate as the rest of the system. 47
Page 1 and 2: SOFT-CORE PROCESSOR DESIGN by Franj
Page 3 and 4: Acknowledgments First, I would like
Page 5 and 6: 5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11 and 12: uilt using techniques proven to be
Page 13 and 14: logic and I/O blocks [11]. Since th
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51: LOAD state, except that a memory wr
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
Page 83 and 84: pipelined implementation. Control-f
Page 85 and 86: not mean that, for example, the ins
Page 87 and 88: There are many paths in each group,
Page 89 and 90: FPGA design flow is a random functi
Page 91 and 92: each be connected to only a single
Page 93 and 94: • The UT Nios design is analyzed
Page 95 and 96: [13] C. Blum and A. Roli, “Metahe
Page 97 and 98: [36] Microchip Technology, “PIC16
Page 99: [60] Altera Corporation, “AN 184:

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