Soft-Core Processor Design - CiteSeer

not mean that, for example, the instruction OP code should not be decoded, but directly used as a
set of control signals. The instruction decoder should be designed to generate as few signals as
possible per datapath unit, which will in many cases be less than the number of bits in the OP
code. For instance, a 4-to-1multiplexer in the datapath can be controlled by only two signals,
while the instruction OP code may have 6 or more bits, all of which may be required to determine
the function of the multiplexer. Depending on the circuit configuration, minimizing the number of
signals feeding the logic may not always reduce the number of LEs used, but in our experience, it
often does.
We considered introducing additional pipeline stages to improve the Fmax. Since a full
implementation of a different pipeline organization is time consuming, we used a simple method
for analyzing the possible benefits of the new pipeline organization. We introduced registers into
the design where the pipeline registers would be added if the new pipeline stage was introduced.
The Fmax of such a design is an upper bound on the Fmax achievable by the new pipeline
organization, because the additional logic has to be introduced to handle newly introduced
hazards and/or stalls, which would likely decrease the Fmax. The cycle count of the new
implementation can be estimated by analyzing newly introduced stalls and estimate the frequency
of the stalls. Although generally this requires a detailed architectural research using simulation,
we used only rough estimates. Our estimates indicated that possible gains in Fmax (described in the
next section) obtained by introducing an additional stage to the pipeline could hardly compensate
for the increase in the cycle count. The performance comparison between the UT Nios and the
Altera Nios, which is a 5-stage pipelined Nios implementation, presented in the previous chapter
suggests that our estimates were correct. However, more research is needed to prove this.
The UT Nios design was tested using several different approaches. In the early stages of the
design process, when the implementation was not fully functional, the assembly programs
executing sequences of instructions that were implemented at that point were used in the
ModelSim simulator. ModelSim [19] supports the simulation of a whole system, including
memories, and provides means for specifying the initial contents of the memories in the system.
In this way, the program can be preloaded into the memory and its execution may be simulated.
Furthermore, the UART model generated by the SOPC builder provides a virtual terminal that
can be used to communicate with the program whose execution is being simulated in ModelSim,
as if the program was actually running on the development board. As more functionality was
added to the UT Nios implementation, small programs could be compiled and executed in the
simulator, and finally on the development board. After the interrupt support was implemented, the
design was tested using simple programs with the UART causing interrupts whenever a key on
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