Soft-Core Processor Design - CiteSeer

5.4.1. Performance
The metric used in the performance comparison is the wall clock time required to execute a
benchmark program. The wall clock time can be expressed as [34]:
T = IC × CPI × C
where IC is the instruction count, CPI is the average number of clock cycles needed to execute an
instruction, and C is the cycle time (i.e. duration of a clock cycle). The instruction count is the
same for both processors, because the same binary programs are run on both systems. Therefore,
the performance will be defined by the number of cycles needed to execute the program (cycle
count) and the cycle time. The best cycle times and the corresponding best Fmax for the four
systems used in the performance comparison are given in Table 5.3. UT Nios has almost 50%
longer cycle time than the Altera Nios for the SRAM system, and 40% longer cycle time for the
ONCHIP system.
Altera Nios
UT Nios
System Cycle Time (ns) Fmax (MHz)
SRAM 8.47 118
ONCHIP 8.59 116
SRAM 12.66 79
ONCHIP 12.03 83
Table 5.3 Cycle time and Fmax of the systems used in performance comparison
All system configurations were run at the clock speed of 50 MHz. Thus, the run times
obtained can be directly used to compare the cycle counts of the two architectures. To obtain the
wall clock run times, the measured times are prorated with the appropriate factor. The comparison
of the SRAM systems based on the Altera and UT Nios is presented in Figures 5.10 and 5.11.
The graphs in the figures show the improvement of UT Nios over the Altera Nios. Both the wall
clock performance ratio and the cycle count ratio are given. Analysis of the cycle count advantage
of the UT Nios for the Loops benchmark shows that the UT Nios implements branch logic better,
since the Loops benchmark executes almost 56% faster in terms of the cycle count. However,
because of the longer cycle time, the advantage of UT Nios over the Altera Nios in terms of the
wall clock time for the Loops benchmark is only 4%. The lower cycle count comes from the
branch logic implementation in UT Nios, where the control-flow instructions are
committed early in the pipeline (in the operand stage), as described in section 4.1.5. The Altera
Nios executes the control-flow instructions less efficiently, which is expected because of the
deeper pipeline.
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