Soft-Core Processor Design - CiteSeer

parameters include the general-purpose register file size, the choice to implement the instruction
decoder in on-chip memory or in logic, the size of the FIFO buffer in the processor’s prefetch
unit, and the starting and vector table memory addresses.
The UT Nios can be used directly in any system generated by the SOPC builder. If the system
contains the 32-bit Altera Nios, the module implementing the Altera Nios can be replaced by the
module implementing the UT Nios. This can be done by simply replacing the Verilog file that
implements the Altera Nios. After setting the UT Nios parameters according to the system
requirements, the system can be compiled in Quartus II and downloaded to an FPGA.
The UT Nios consists of two main modules; datapath and control unit. The processor datapath
defines interconnections between the processor modules and defines how data propagates
between the pipeline stages. The control unit is a finite state machine that produces the control
signals for modules in the datapath. In the sections that follow we present high-level
implementation details of the UT Nios. For the low-level details, the UT Nios Verilog code
should be consulted.
4.1. UT Nios Datapath
The structure of the UT Nios datapath is presented in Figure 4.1. The datapath is organized in
4 pipelined stages: fetch (F), decode (D), operand (O), and execute (X). The fetch stage consists
of a prefetch unit that performs functions of the instruction master, stores the instruction fetched
from the memory into a FIFO buffer, and forwards the instructions to the decode stage. In the
decode stage, instructions are decoded and the operands from the general-purpose register file are
read. The datapath shown in Figure 4.1 implements the instruction decoder in on-chip memory. In
the operand stage, the operands to be used in the computation are selected from the possible
sources. Various instructions use various operands, including register and immediate operands.
The immediate operands are formed from the immediate value encoded in the instruction word by
sign-extending it, multiplying it by a constant, or concatenating it to the value in the K register.
Branching and updating the K register is also performed in the operand stage. The execute stage
performs computations, memory operations, and conditional instructions; it commits the
operation results to the general-purpose register file and control registers. All instructions except
the memory operations and the control-flow instructions take one cycle to commit their result.
The latency of the memory operations depends on the data memory latency, so these instructions
generally take 2 or more cycles to commit if the synchronous memory is used.
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