Soft-Core Processor Design - CiteSeer

The Stratix FPGA device family has a much more complex structure than the general FPGA
described in section 2.1. In addition to logic blocks, routing, and I/O blocks, Stratix devices also
contain DSP blocks, phase-locked loops (PLLs), and memory blocks. As already mentioned,
memory is the key component that makes an FPGA suitable for SOPC designs. Devices in the
Stratix family contain anywhere from 920,448 to 7,427,520 memory bits. Several different types
of memory blocks are available, each one suited to a particular application. Memory blocks
support several modes of operation, including simple dual-port, true dual-port, and single-port
RAM, ROM, and FIFO buffers. Some memory block types can be initialized at the time the
device is configured [12]. In this case the memory initialization bits are a part of the FPGA
programming file.
All the memory available in Stratix devices is synchronous. All inputs to a memory block are
registered, so the address and data are always captured on a clock edge. Outputs can be registered
for pipelined designs. Synchronous memory offers several advantages over asynchronous
memory. Synchronous memory generates a write strobe signal internally, so there is no need for
external circuitry. Performance of the synchronous memory is the same or better than
asynchronous memory, providing that the design is pipelined [17].
Quartus II provides a set of tools for circuit designs targeting Altera programmable devices.
These tools include design editors, compilation and simulation tools, and device programming
software. Design specification can be entered using one or more of the following formats:
schematic entry, VHDL, Verilog HDL, Altera HDL (AHDL), EDIF netlist, and Verilog Quartus
Mapping File (VQM) netlist. AHDL is an Altera specific HDL integrated into Quartus II. EDIF
and VQM are two netlist specification formats [18]. Netlist input formats are useful when a third
party synthesis tool is used in the design flow. Output of the third party tool can be fed to
Quartus, which performs placement and routing (also called fitting in Quartus terminology) for
Altera FPGAs. This is especially useful for legacy designs that include language constructs or
library components specific to other synthesis tools. Various parameters guiding the compilation
process can be set, and the process can be automated using scripting.
Quartus II includes a library of parameterizable megafunctions (LPM), which implement
standard building blocks used in digital circuit design. Library megafunctions may be
parameterized at design time to better suite the needs of a system being designed. Using the
megafunctions instead of implementing the custom blocks reduces the design time. The
megafunctions may be implemented more efficiently in the target FPGA than the custom design,
although that is not necessarily always the case [16]. There are two ways a megafunction can be
included in HDL design. It may be explicitly instantiated as a module, or it can be inferred from
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