Soft-Core Processor Design - CiteSeer

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�� ©¨�� d_wait is lowered by the bus logic, and the data has to be captured on the positive edge of the clock. A simplified state diagram of the control unit FSM is shown in Figure 4.4. The figure only shows the state changes with respect to several input signals. The actual state machine has 30 input and 13 output signals. However, it is not necessary to understand all of these signals to understand the basic behaviour of the FSM. Most of the FSM input signals describe an instruction in the execute stage, because most instructions require dynamic control signals in this stage, where they commit their results. The exceptions are the control-flow instructions, which commit in the operand stage, so the FSM input signals concerning the control-flow instructions become active when the instruction is in the operand stage. � �� § On system reset, the FSM enters the R & X state (Read an instruction and execute it). Most instructions are handled in the R & X state, except for all load, store and skip instruction variants, and the TRAP instruction. When a load instruction reaches the execute pipeline stage, a memory read request is issued, the pipeline is stalled, and the FSM enters the LOAD state. The FSM remains in the LOAD state until the d_wait bus signal becomes low, signalling that the valid data is available on the bus. At this point, a register write signal is asserted to capture the incoming data, and the FSM returns to the R & X state. Operation of the STORE state is similar to the 44 �� ¢¡¤£¦¥¨§ � �� £ ��¨�� ¨�� Figure 4.4 Control unit FSM state diagram ¥��
LOAD state, except that a memory write request is issued and the data is not written to the register file. If a memory operation, either load or store, accesses the memory with no latency, the FSM never enters the respective state, because the memory operation commits in a single cycle, like most other operations. When a skip instruction reaches the execute stage, its condition is verified. The control unit is able to verify the skip condition because the values of the condition code flags, and a register operand, are forwarded to the control unit. These values are needed because the skip instruction SKPS tests the condition on flag values, while instructions SKPRZ, SKPRNZ, SKP1, and SKP0 test the values of the register operand. If the skip condition is satisfied, the FSM enters the C_PFX state (Check for PFX). It remains in the C_PFX state if the instruction in the execute pipeline stage is a PFX instruction. While the FSM is in the C_PFX state, any instruction that reaches the execute stage does not commit its results. Therefore, the instruction that follows the PFX will not commit its result, which is required by the semantics of the PFX instruction. After the instruction following the PFX retires from the execute stage, the FSM returns to the R & X state. If a TRAP instruction is in the execute pipeline stage, a memory read request for a vector table entry is issued, and the FSM enters the TRAP state. The FSM remains in the TRAP state until the memory responds with valid data. At that point, pipeline registers and the prefetch unit are flushed, and new instructions are fetched from the address retrieved from the vector table. The FSM returns to the R & X state, and the operation of the pipeline resumes. Other instructions do not require additional states to be handled properly. If a control-flow instruction is in the operand pipeline stage, and the FSM is in the R & X state, the prefetch unit is flushed and the FSM remains in the R & X state. If the next instruction is not available from the prefetch unit, the pipeline is stalled, and the state machine stays in the R & X state. If a control-flow instruction is encountered while the FSM is in the LOAD or STORE state, the prefetch unit is flushed when the memory lowers the d_wait signal. If the control-flow instruction is encountered while the FSM is in the TRAP state, the control-flow instruction is not executed, because the TRAP instruction modifies the control flow itself and does not have the delay slot behaviour. I/O and software interrupts are handled by inserting the TRAP instruction with the appropriate interrupt number into the pipeline. In case of a software interrupt, all instructions following the instruction causing the interrupt are flushed from the pipeline and replaced by NOPs. The operation of the pipeline resumes until the inserted TRAP instruction reaches the execute stage, where it is handled like a normal TRAP instruction. 45
Page 1 and 2: SOFT-CORE PROCESSOR DESIGN by Franj
Page 3 and 4: Acknowledgments First, I would like
Page 5 and 6: 5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11 and 12: uilt using techniques proven to be
Page 13 and 14: logic and I/O blocks [11]. Since th
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49: individual bits (e.g. flags), and g
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
Page 83 and 84: pipelined implementation. Control-f
Page 85 and 86: not mean that, for example, the ins
Page 87 and 88: There are many paths in each group,
Page 89 and 90: FPGA design flow is a random functi
Page 91 and 92: each be connected to only a single
Page 93 and 94: • The UT Nios design is analyzed
Page 95 and 96: [13] C. Blum and A. Roli, “Metahe
Page 97 and 98: [36] Microchip Technology, “PIC16
Page 99: [60] Altera Corporation, “AN 184:

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