Soft-Core Processor Design - CiteSeer

The table rows correspond to consecutive clock cycles. In the first clock cycle, instruction 1 is
in the execute stage, about to commit its result to register %r3. In the second cycle, the LAST
value contains the value written into register %r3. The load instruction (2) is in the execute stage,
and the add instruction (3) is in the operand stage. For this example, we assume that the data
memory has no latency. Therefore, in the normal pipeline operation, the add instruction (3) would
use the value of register %r3 stored in the LAST register, because it is the most recently written
value, and the value of the %r4 register that is just being written, because the load instruction
precedes the add instruction in the sequential program order. Hence, the register S_LAST is not
needed.
The last row in the table demonstrates a case when the pipeline stalls because the prefetch unit
does not have the next instruction ready. This may happen if the instructions and data reside in
the same memory module, in which case the instruction and data master conflict if they access the
memory at the same time. The load instruction (2) has committed its result at the end of the
second cycle because the memory holds the valid data only until the rising edge of the clock,
when the processor has to capture it. However, this overwrites the value in the LAST register
with (r4, 7), assuming that the memory read result is 7. If there was no S_LAST register, the add
instruction would use the stale value of register %r3. Keeping both LAST and S_LAST values
enables the add instruction to use the most recently written data and preserve the semantics of the
original program order.
Formally, the data forwarding logic performs the following steps to ensure that the correct
operand values are always used:
1. If the instruction in the execute stage writes the register that is being read, use the value
that is being written
2. Else, if the register being read has been written last, use the saved value (LAST)
3. Else, if the register being read has been written second last, use the second last saved
value (S_LAST)
4. Else, use the value read from the register file
These steps ensure that the most recently written data is always used, which corresponds to the
behaviour specified by the original program order.
4.1.9. Control Registers
The control registers module implements the logic necessary to maintain the processor status
in the control register set. Control registers %ctl3 to %ctl7 are implemented using the on-chip
memory. Registers STATUS, ISTATUS, and WVALID are implemented in logic, because
42