Soft-Core Processor Design - CiteSeer

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Chapter 7 Conclusions and Future Work The capabilities of FPGAs have increased to the level where it is possible to implement a complete computer system on a single FPGA chip. The main component in such a system is a soft-core processor. The Nios soft-core processor is intended for implementation in Altera FPGAs. In this thesis project a Verilog implementation of the Nios architecture has been developed, called UT Nios. Performance of UT Nios has been investigated and compared to that of the Altera Nios. Performance analysis has shown that, although the Altera and UT Nios implementations are quite different, their performance is similar. <strong>Design</strong> analysis has shown that although there is little room for improvement in the current UT Nios organization, there is a lot of room for experimenting with different processor organizations and architectural parameters. The thesis offers the following contributions: • UT Nios implementation of the Nios architecture is described. The incremental design methodology used in the UT Nios design is described. This methodology resulted in an unconventional implementation with the performance comparable to the original implementation from Altera. • UT Nios benchmark set suitable for evaluation of the soft-core processor based systems is presented. The benchmark set was selected among the existing benchmarks and supplemented with benchmarks suitable for performance analysis of the Altera and UT Nios. All benchmarks were adapted for use on the Nios based systems. • A detailed analysis of the UT Nios performance and a comparison with the Altera Nios was performed and the results are presented. The results show that the application performance varies significantly with various architectural parameters. A single architectural parameter that influences performance the most is the size of the general-purpose register file. The results indicate that many applications perform worse on the system with the windowed register file of small size than on the same system that does not use register windows capabilities, but uses only a single register window. The performance comparison of the UT and Altera Nios shows that both implementations achieve similar performance. 86
• The UT Nios design is analyzed in detail. Possible design improvements are suggested and discussed. The CAD tools used in this thesis are described and the characteristics of the tools relevant for the methodology used are discussed. Finally, possible improvements in the design tools are suggested. The UT Nios Verilog code and the source code of the UT Nios benchmark set will be made publicly available on the author’s web site in the near future. 7.1. Future Work This thesis leaves a lot of room for future work. First, optional Nios architecture components like caches and hardware multiplication could be implemented. More research is needed on the possible pipeline organizations that may offer better performance. Furthermore, the results of the thesis could be used to consider some changes in the Nios instruction set architecture that may lead to superior performance or lower area utilization. The UT Nios benchmark set should be converted to the format proposed in [57], and new programs should be added to it. We see UT Nios as a great educational tool for use in the computer architecture courses. Students could easily modify the architectural parameters, and see the effects immediately on a real system. We believe that such a methodology would be more educational than the current simulation-based methods. 87
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SOFT-CORE PROCESSOR DESIGN by Franj
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Acknowledgments First, I would like
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5.1.2. Development Tools ..........
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Chapter 1 Introduction Since their
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Chapter 2 Background Soft-core proc
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uilt using techniques proven to be
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logic and I/O blocks [11]. Since th
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timing-driven [11]. Although simula
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the HDL coding style. To ensure tha
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3.1. Nios Architecture The Nios ins
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esult of a read operation from thes
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satisfied the instruction that foll
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Most instructions take 5 cycles to
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contents of the register window wil
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needed, the master asserts the flus
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There are several ways in which use
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code) is provided [47]. Both printf
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memory address has to be set in the
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parameters include the general-purp
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Similarly, the control-flow instruc
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Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
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Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
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Page 85 and 86: not mean that, for example, the ins
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Page 95 and 96: [13] C. Blum and A. Roli, “Metahe
Page 97 and 98: [36] Microchip Technology, “PIC16
Page 99: [60] Altera Corporation, “AN 184:
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