Soft-Core Processor Design - CiteSeer

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[25] Altera Corporation, “Avalon Bus Specification, Reference Manual,” [Online Document], 2003 July, [Cited 2004 February 11], Available HTTP: http://www.altera.com/literature/manual/mnl_avalon_bus.pdf [26] E. David, A Network Processor Platform Implemented in Programmable Hardware, Master’s Thesis, Faculty of California Polytechnic State University, San Luis Obispo, CA, 2003. [27] Y. Thoma and E. Sanchez, “CoDeNios: A Function-Level Co-Design Tool,” in Proc of the Workshop on Computer Architecture Education, Anchorage, AK, 2002, pp.73-78. [28] J. Kairus, J. Forsten, M. Tommiska, and J. Skyttä, “Bridging the Gap Between Future Software and Hardware Engineers: A Case Study Using the Nios Softcore Processor,” In Proc. of the 33rd ASEE/IEEE Frontiers in Education Conference, Boulder, CO, 2003, pp. F2F-1 – F2F-5. [29] T. S. Hall and J. O. Hamblen, “System-on-a-Programmable-Chip Development Platforms in the Classroom,” To appear in IEEE Transactions on Education, 2004, [Online Document, Cited 2004 February 29], Available HTTP: http://www.ece.gatech.edu/~hamblen/papers/SOC_top.pdf [30] Altera Corporation, “What Customers & Industry Analysts Are Saying About the Nios Embedded Processor,” [Online Document, Cited 2004 February 29], Available HTTP: http://www.altera.com/corporate/news_room/customer_quotes/nios/cqt-nios.html [31] Microtronix Systems Ltd., “MicroC/OS-II RTOS Development Kit,” [Online Document, Cited 2004 February 29], Available HTTP: http://www.microtronix.com/products/microcos.html [32] SPARC International Inc., “The SPARC Architecture Manual, Version 8,” [Online Document], 1992, [Cited 2004 February 11], Available HTTP: http://www.sparc.com/standards/V8.pdf [33] Altera Corporation, “Nios Features: CPU Architecture,” [Online Document, Cited 2004 February 12], Available HTTP: http://www.altera.com/products/ip/processors/nios/features/nio-cpu_architecture.html [34] J. L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 3 rd . ed., Morgan Kaufmann Publishers: San Francisco, CA, 2003. [35] Internet FAQ Archives, “What is the PDP-8 instruction set?” [Online Document, Cited 2004 February 12], Available HTTP: http://www.faqs.org/faqs/dec-faq/pdp8/section-3.html 90
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Page 1 and 2:
SOFT-CORE PROCESSOR DESIGN by Franj
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Acknowledgments First, I would like
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5.1.2. Development Tools ..........
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Chapter 1 Introduction Since their
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Chapter 2 Background Soft-core proc
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uilt using techniques proven to be
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logic and I/O blocks [11]. Since th
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timing-driven [11]. Although simula
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the HDL coding style. To ensure tha
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3.1. Nios Architecture The Nios ins
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esult of a read operation from thes
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satisfied the instruction that foll
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Most instructions take 5 cycles to
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contents of the register window wil
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needed, the master asserts the flus
Page 31 and 32:
There are several ways in which use
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code) is provided [47]. Both printf
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memory address has to be set in the
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parameters include the general-purp
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Similarly, the control-flow instruc
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the logic resources may be more cri
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simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
Page 83 and 84: pipelined implementation. Control-f
Page 85 and 86: not mean that, for example, the ins
Page 87 and 88: There are many paths in each group,
Page 89 and 90: FPGA design flow is a random functi
Page 91 and 92: each be connected to only a single
Page 93 and 94: • The UT Nios design is analyzed
Page 95: [13] C. Blum and A. Roli, “Metahe
Page 99: [60] Altera Corporation, “AN 184:
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