Soft-Core Processor Design - CiteSeer

functionality equivalent to the Altera Nios and achieves the performance comparable to that of
the Altera Nios. This thesis provides the details of the steps involved in the UT Nios
development, and discusses the design decisions and trade-offs involved. The design cycles in the
FPGA design methodology are much shorter than for ASICs. Therefore, the design decisions
during the UT Nios development process were guided by the feedback from the previous steps.
The thesis shows how this methodology can be used for incremental design improvement.
The UT Nios benchmark set is defined to investigate the performance of the Altera and UT
Nios. The influence of various processor parameters on the performance of both UT and Altera
Nios is investigated, and their performance is compared. The results indicate that the performance
of different applications varies significantly depending on the architectural parameters. Different
applications also achieve different performance when running on the Altera and UT Nios,
although the performance of the two implementations is similar on average. A comparison of the
Altera and UT Nios shows that comparable performance can be achieved by using two different
processor organizations. The thesis discusses the UT Nios design and analyzes the prospects for
design improvements and other future work.
The thesis is organized as follows. Chapter 2 gives an overview of related work, the FPGA
technology and the design flow. In Chapter 3, the Nios architecture is presented, along with the
supporting software tools. Chapter 4 describes the details of the UT Nios architecture.
Experimental results and the methodology used to measure the performance of UT Nios are
presented in Chapter 5. In Chapter 6, a discussion of the design and experimental results is given.
Chapter 7 concludes the thesis and gives an overview of the future work.
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