Soft-Core Processor Design - CiteSeer

Most instructions take 5 cycles to execute. Execution time of the MUL instruction varies from
5 to 8 cycles, depending on the FPGA device it is implemented in. MSTEP and shift instructions
take 6 cycles to execute. Memory operations take 5 or more cycles to execute, depending on the
memory latency and bus arbitration. Although each instruction takes at least 5 cycles to execute,
due to pipelined execution, one instruction per cycle will finish its execution in the ideal case. In
reality, less than one instruction will commit per cycle, since some instructions take more than 5
cycles to execute. The pipeline implementation is not visible to user programs, except for the
instructions in the delay slot, and the WRCTL instruction. An instruction in the delay slot
executes out of the original program order. Any WRCTL instruction modifying the STATUS
register has to be followed by a NOP instruction. NOP is a pseudo instruction implemented as
MOV %r0, %r0.
Systems using the Nios processor can use both on- and off-chip memory for instruction and
data storage. Memory is byte addressable, and words and halfwords are stored in memory using
little-endian byte ordering. All memory addresses are word aligned for 32-bit Nios, and halfword
aligned for 16-bit Nios. Special control signals, called byte-enable lines, are used when a partial
word has to be written to the memory. Systems using off-chip memory can use the on-chip
memory as instruction and data caches. Caches are direct-mapped with write-through write
policy for the data cache. The instruction cache is read-only. If a program writes to the instruction
memory, the corresponding lines in the instruction cache have to be invalidated. Cache support is
only provided for the 32-bit Altera Nios.
Several Nios datapath parameters can be customized. The pipeline can be optimized for speed
or area. The instruction decoder can be implemented in logic or in memory. Implementation in
logic is faster, while memory implementation uses on-chip memory and leaves more resources for
user-logic. According to [38], both 16- and 32-bit Nios can run at clock speeds over 125 MHz.
This number varies depending on the target FPGA device.
3.1.4. Interrupt Handling
There are three possible sources of interrupts in the Nios architecture: internal exceptions,
software interrupts, and I/O interrupts. Internal exceptions occur because of unexpected results in
instruction execution. Software-interrupts are explicit calls to trap routines using TRAP
instruction, often used for operating system calls. I/O interrupts come from I/O devices external
to the Nios processor, which may reside both on and off-chip.
The Nios architecture supports up to 64 vectored interrupts. Internal exceptions have
predefined exception numbers, while software-interrupts provide the exception number as an
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