Soft-Core Processor Design - CiteSeer

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Chapter 4 UT Nios Architectural research has traditionally been done by using simulators to evaluate the performance of proposed systems because building a prototype of a processor in an ASIC is expensive and time consuming. <strong>Soft</strong>-core processors are fully described in software and implemented in programmable hardware, and thus easy to modify. This means that architectural research on soft-core processors can be performed on actual hardware, while the architecture parameters are changed by modifying the software. The UT Nios soft-core processor was developed to get insight into this process and to explore the performance of the Nios architecture. UT Nios was implemented using Verilog HDL. Verilog was chosen over VHDL because of its increasing popularity, and because it is simpler to use and understand. UT Nios is customizable through the use of define and defparam Verilog statements. Its design is optimized for implementation in FPGAs in the Stratix device family. Stratix was chosen because of the high amount of memory it contains, which makes it suitable for soft-core processor implementation. Another reason for choosing Stratix is the availability of the Nios Development Kit, Stratix Edition [50]. Although Altera also provides a Cyclone Edition [51] and an Apex Edition [52] of the Nios Development Kit, Stratix is a newer device family, which is likely to be used in Nios systems. While we focus on a single FPGA device family, UT Nios can easily be adapted for use on any system that supports design entry using Verilog. The choice of Stratix as a target FPGA device family had great influence on the design of UT Nios. As mentioned previously in section 2.4, all the memory available in Stratix FPGAs is synchronous. Therefore, any read from the memory will incur a latency of at least one clock cycle, because the data address cannot be captured before the rising edge of the clock [25]. Although the use of the synchronous memory increases the throughput in pipelined designs, any design using memory necessarily has to be pipelined. For instance, the Nios architecture has a large general-purpose register file. Implementing this file in logic is impractical due to the register file size. Therefore, the register file has to be implemented in the synchronous memory, and the design has to be pipelined. The Stratix documentation [17] suggests that asynchronous mode may be emulated by clocking the memory using an inverted clock signal (with respect to the clock controlling the rest of the logic). Memory data would then be available after a half of the clock cycle. However, this imposes tight constraints on the timing of the rest of the logic. A 28
memory address has to be set in the first half of the cycle, while the data from the memory is only available in the second half of the cycle. Depending on the system, logic delays may not be balanced around the memory block, in which case the clock’s duty cycle has to be adjusted. Since the asynchronous emulation mode imposes undesirable constraints on the system, synchronous memory should be used whenever possible [17]. Using synchronous memory in a design does not limit the design’s use to Stratix FPGAs only, because most devices that support asynchronous memory also support the synchronous memory operation [53]. Several versions of UT Nios have been implemented. Initially, a 16-bit processor that executed all instructions in a single clock cycle (not including fetching the instruction from the memory) was implemented. This implementation includes an instruction prefetching unit that communicates instructions to other processor modules through the instruction register (IR). Therefore, it may be considered a 2-stage pipelined implementation. Critical paths of the implementation were analyzed, and the results were used to guide the development of a 3-stage pipelined version, and subsequently a 4-stage pipelined version. Finally, this architecture was extended to a 32-bit 4-stage pipelined version of UT Nios by increasing the datapath width and accommodating the differences in the instruction sets of 16- and 32-bit Nios architectures. In the rest of the thesis we use the term UT Nios for the 4-stage pipelined version of the 32-bit UT Nios. We focus on the 4-stage pipelined version because of its performance advantage over other versions. We focus on the 32-bit architecture, because it is more likely to be used in high performance applications. The organization of the 4-stage pipelined version of the 16-bit UT Nios is similar to the 32-bit UT Nios described. The development process and the performance of various UT Nios versions will be discussed in Chapter 6. UT Nios described in this chapter differs from the 32-bit Nios architecture [23] in the following ways: • there is no support for instruction and data cache • there is no multiplication support in hardware • there is no support for the OCI debug module and the non-maskable interrupt • I/O interrupts are not accepted in cycles in which a control-flow instruction is in stages 3 or 4 of the pipeline • I/O interrupts are not accepted in a cycle in which SAVE, RESTORE, or WRCTL instructions are in stage 3 of the pipeline • a NOP instruction has to be inserted between pairs of the following instructions: SAVE after SAVE, SAVE after RESTORE, RESTORE after SAVE, and RESTORE after RESTORE 29
Page 1 and 2: SOFT-CORE PROCESSOR DESIGN by Franj
Page 3 and 4: Acknowledgments First, I would like
Page 5 and 6: 5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11 and 12: uilt using techniques proven to be
Page 13 and 14: logic and I/O blocks [11]. Since th
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33: code) is provided [47]. Both printf
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
Page 83 and 84: pipelined implementation. Control-f
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not mean that, for example, the ins
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There are many paths in each group,
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FPGA design flow is a random functi
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each be connected to only a single
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• The UT Nios design is analyzed
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[13] C. Blum and A. Roli, “Metahe
Page 97 and 98:
[36] Microchip Technology, “PIC16
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[60] Altera Corporation, “AN 184:
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