Soft-Core Processor Design - CiteSeer

Figure 5.1 shows that the performance of the ONCHIP system is the best for all benchmarks
when the FIFO buffer has a unit size. The performance drop with the increasing buffer size
results from the memory access conflicts, because both data and instructions reside in the same
memory. If both instruction and data master request the memory access at the same time, the bus
arbitration logic grants the access to one of the masters, while wait states are generated for the
other. This is obvious from Figure 5.1, which shows that the Memory test benchmark suffers the
biggest performance penalty because of the increasing FIFO buffer size. The Pipeline-Memory
benchmark, which reads the data from the BOOT memory that is not accessed by the instruction
master while the program is running, does not suffer any performance penalty. At the same time,
the Pipeline-Memory benchmark that reads the data from the PROGRAM memory, suffers mildly
from increasing the FIFO buffer size.
Figures 5.2 and 5.3 show how the benchmark performance varies with the FIFO buffer size on
the SRAM system. The best performance for all benchmarks is achieved with the buffer size 2.
Similar to the ONCHIP system, further increases in the buffer size hurt the performance. The
Pipeline test benchmark benefits the most from increasing the FIFO buffer size to two registers,
Speedup Over Buffer Size 1
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
Loops
Size = 2 Size = 3 Size = 4 Size = 15
Memory
Pipeline
Pipeline-Memory
(BOOT)
Figure 5.2 Performance of the test and toy benchmarks vs. the FIFO buffer size on the
SRAM system
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Pipeline-Memory
(PROGRAM)
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