Soft-Core Processor Design - CiteSeer

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the branch. In such a case, instructions already in the FIFO buffer together with any pending memory reads are flushed, and a memory read to the branch target address is issued in the next cycle. Fetching instructions from the instruction memory will take at least one clock cycle if the synchronous memory is used, which makes for a total of at least a two-cycle branch penalty. Although Altera provides the LPM FIFO megafunction, the FIFO buffer in the prefetch unit is described using Verilog language. The implementation of the instruction decoder requires the instruction from the prefetch unit to be available whenever the prefetch unit has a new instruction ready, even if the read request for the new instruction (cpu_wants_to_read) is not asserted. The read request line is used only to acknowledge that the currently available data has been read, and the new data should be supplied. This mode of operation of the FIFO megafunction is called show-ahead mode. Altera’s LPM FIFO megafunction does not support show-ahead mode for designs targeting Stratix [54], so the custom FIFO buffer was implemented. The fetch and decode pipeline stages are synchronized using two handshake signals; cpu_wants_to_read, and prefetch_unit_has_valid_data. When the prefetch_unit_has_valid_data signal is set, the instruction on the output of the prefetch unit is valid. After the instruction decoder reads the instruction, it asserts the cpu_wants_to_read line to acknowledge that the instruction has been read, and that a new instruction should be supplied. On the next rising edge of the clock, the prefetch unit either supplies the next instruction and keeps the prefetch_unit_has_valid_data line asserted, or it deactivates the line if the next instruction is not ready. In the absence of stalls, both handshake lines will be continuously asserted and instructions will leave the fetch stage one per cycle. If the prefetch unit does not have the next instruction ready, the pipeline is stalled until the next instruction is fetched from the instruction memory. The prefetch unit communicates instructions to the decode stage of the pipeline both directly and through the instruction register (IR). The functionality of the decode stage is presented in the following two sections. 4.1.2. Instruction Decoder The instruction decoder produces a set of signals, called the control word, that define the operations the pipeline modules need to perform to implement the decoded instruction. The instruction decoder may be completely implemented in logic, or the on-chip memory may be used to implement a large portion of the decoder. It can be implemented in the memory that stores a control word for each instruction in the instruction set. This memory will be referred to as the instruction decoder (ID) memory. Depending on the system requirements, either the memory or 34
the logic resources may be more critical, so the noncritical resource may be used to implement the instruction decoder. Figure 4.2 Ri8 and Rw instruction formats [23] The UT Nios uses the same instruction encoding as the Altera Nios to ensure the binary code compatibility. The ID memory is addressed using the instruction OP code. Since the Nios instruction encoding uses many different instruction formats, it would be impractical to use memory for decoding all of the instructions. The reason is that some instruction formats use 11-bits wide OP codes, while others use only 3-bits wide OP codes, as shown in Figure 4.2 [23]. Instruction format Ri8 uses only the highest 3 bits for the OP code, while the remaining bits are used for an 8-bit immediate operand (IMM8) and a 5-bit register address (A). The Rw instruction format uses 11 bits (op6 and op5w) for the OP code, which is also the maximum number of bits used for the OP code by any instruction format. The remaining 5 bits define the register address. Using an ID memory addressed with 11 bits wide OP code would require a memory size of 2K control words. Many of the control words would be redundant. Since the Ri8 instruction format uses only the highest 3 bits for the OP code, the 8 immediate operand bits would also be used to address the ID memory. Since the operation of the datapath is independent of the immediate values, there would be 2 8 identical control words stored in the ID memory. To reduce the amount of memory used, the regularities in the instruction encoding are exploited. All instructions using the Rw instruction format have an identical op6 field (i.e. the highest 6 bits) of the instruction word. Individual instructions are identified by the op5w field value. Therefore, a memory of 2 5 control words is used to encode these instructions. Most of the remaining instructions can be identified by the 6 highest bits of the instruction word. Therefore, another memory of 2 6 control words is used. This mapping will still result in some redundant memory words. However, only 96 control words need to be stored in the memory, as opposed to 2K control words when using the naive approach. Since not all the instructions can be identified by the highest 6 bits of the instruction word, the proposed mapping also produces conflicts resulting from two or more instructions mapping to the same location in the ID memory. 35
Page 1 and 2: SOFT-CORE PROCESSOR DESIGN by Franj
Page 3 and 4: Acknowledgments First, I would like
Page 5 and 6: 5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11 and 12: uilt using techniques proven to be
Page 13 and 14: logic and I/O blocks [11]. Since th
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39: Similarly, the control-flow instruc
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
Page 83 and 84: pipelined implementation. Control-f
Page 85 and 86: not mean that, for example, the ins
Page 87 and 88: There are many paths in each group,
Page 89 and 90: FPGA design flow is a random functi
Page 91 and 92:
each be connected to only a single
Page 93 and 94:
• The UT Nios design is analyzed
Page 95 and 96:
[13] C. Blum and A. Roli, “Metahe
Page 97 and 98:
[36] Microchip Technology, “PIC16
Page 99:
[60] Altera Corporation, “AN 184:
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