Soft-Core Processor Design - CiteSeer

logic and I/O blocks [11]. Since the content of SRAM cells is lost when the device is not
powered, the configuration needs to be reloaded into the device on each power-up. This is done
using a configuration device that loads the configuration stored in some form of non-volatile
memory.
Programmability of FPGAs comes at a price. Resources necessary for the programmability
take up chip area and consume power. Therefore, circuits implemented in FPGAs take up more
area and consume more power than in equivalent ASIC implementations. Furthermore, since the
routing in FPGAs is achieved using programmable switches, as opposed to metal wires in ASICs,
circuit delays in FPGAs are higher. Because of that, care has to be taken to exploit the resources
in an FPGA efficiently. Circuit speed is important for high-throughput applications like Digital
Signal Processing (DSP), while power is important for embedded applications. CAD tools are
used by the designer to meet these requirements.
2.3. FPGA Design Flow
Designing a complex system targeting FPGAs would be virtually impossible without CAD
tools. The CAD tools convert the user’s specification into an FPGA configuration that
implements the specified functionality, while optimizing one or more design parameters.
Common optimizations include reducing the chip area, increasing the speed, and reducing the
power usage. The CAD tools perform a set of steps to map the design specification to an FPGA.
Figure 2.2 shows the design flow of typical CAD tools targeting FPGAs [11].
Input to a CAD tool is a high-level circuit description, which is typically provided using a
hardware description language (HDL). VHDL (Very High Speed Integrated Circuit Hardware
Description Language) and Verilog HDL are the two most popular HDLs in use today. An HDL
circuit description is converted into a netlist of basic gates in the synthesis step of the design flow.
The netlist is optimized using technology-independent logic minimization algorithms. The
optimized netlist is mapped to the target device using a technology-mapping algorithm.
A minimization algorithm ensures that the circuit uses as few logic blocks as possible. Further
optimizations that exploit the structure of the underlying FPGA are also performed. For instance,
some FPGAs group logic blocks in clusters, with high connectivity among the blocks inside the
cluster, and less routing resources connecting logic blocks in different clusters. This is usually
referred to as hierarchical routing. The synthesis tool will use information on the cluster size and
connectivity to map logic that requires many connections inside a cluster. This optimization is
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