Soft-Core Processor Design - CiteSeer

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immediate operand. The interrupt number for an I/O interrupt is provided through a 6-bit input signal. In most systems, the automatically generated Avalon bus provides this functionality, so the I/O devices need to provide only a single output for an interrupt request. Interrupt priorities are defined by exception numbers: the lowest exception number has the highest priority. Internal exceptions can only occur as a result of executing SAVE and RESTORE instructions. If the SAVE instruction is executed while the lowest valid register window is in use (CWP = LO_LIMIT), a register window underflow exception occurs. Register window overflow exception, on the other hand, happens when the highest valid register window is in use (CWP = HI_LIMIT), and the RESTORE instruction is executed. Register window underflow and overflow exceptions have exception numbers 1 and 2, respectively. These exceptions ensure that the data in the register window is not overwritten due to the underflow or overflow of the CWP value. Register window underflow/overflow exceptions can be handled in two ways: the user application can terminate with an error message, or the code that virtualizes the register file (CWP Manager) can be executed. The CWP Manager stores the contents of the register file to memory on the window underflow, and restores the values from the memory on the window overflow exception. The CWP Manager is included in the Nios Software Development Kit (SDK) library by default. Only SAVE and RESTORE instructions can cause register window underflow/overflow exceptions. Modifying the CWP field using the WRCTL instruction cannot cause exceptions. All interrupts, except the interrupt number 0 and software interrupts, are handled equivalently. First of all, an interrupt is only processed if interrupts are enabled (IE bit in the status register is set), and the interrupt priority is higher than the current interrupt priority (interrupt number is less than the IPRI field in the status register). Interrupt processing is performed in several steps. First, the STATUS control register is copied into the ISTATUS register. Next, the IE bit in the STATUS register is set to 0, CWP is decremented (opening a new register window), and the IPRI field is set to the interrupt number of the interrupt being processed. At the same time, the return address is stored in general-purpose register %o7. The return address is the address of the instruction that would have executed if the interrupt had not occurred. Finally, the address of the interrupt handling routine is fetched from the corresponding entry in the vector table, and the control is transferred to that address. Interrupt handling routines can use registers in the newly opened window, which reduces the interrupt handling latency because the handler routine does not need to save any registers. The only interrupt that does not open a new window is the register window overflow exception. The CWP value remains at HI_LIMIT when the register window overflow exception occurs. This is acceptable, because the program will either terminate or the 20
contents of the register window will be restored from the memory. Interrupt handler routines use the TRET instruction with register %o7 as an argument to return the control to the interrupted program. Before returning control, the TRET instruction also restores the STATUS register from the ISTATUS register. If the IE bit was set prior to the occurrence of the interrupt, then restoring the STATUS register effectively re-enables interrupts, since the STATUS register was saved before the interrupts were disabled. Software interrupts are processed regardless of the values of IE and IPRI fields in the status register. The return address for the software interrupt is the address of the instruction immediately following the TRAP, since the TRAP instruction does not have the delay slot behaviour. Software interrupts are in other respects handled as described above. Interrupt number 0 is a non-maskable interrupt, and its behaviour is not dependent on IE or IPRI fields. It does not use the vector table entry to determine the interrupt handler address. It is used by the Nios on-chip instrumentation (OCI) debug module, which is an IP core designed by First Silicon Solutions (FS2) Inc [39]. The OCI debug module enables advanced debugging by connecting directly to the signals internal to the Altera Nios CPU [23]. Exceptions do not occur if an unused OP code is issued. An unused OP code is treated as a NOP by the Altera Nios [40]. Issuing the MUL instruction on a 32-bit Altera Nios that does not implement the MUL instruction in hardware does not cause an exception, and the result is undefined [37]. Similarly, the result of the PFXIO operation immediately before any instruction other than LD or LDP is undefined [23]. Available documentation does not specify the effect of issuing other optional instructions (e.g. RLC and RRC) when there is no appropriate support in hardware. Interrupts are not accepted when the instruction in the branch delay slot is executed because that would require saving two return addresses: the branch target address and the delay slot address. Although this behaviour is not specified in the documentation, it follows directly from [41]. To save logic resources on the FPGA chip, interrupt handling can optionally be turned off if it is not required by the particular application. In this section we described the main features of the Altera Nios soft-core processor architecture. The processor is connected to other system components by using the Avalon bus [25]. The main characteristics of the Avalon bus are presented in the next section. 21
Page 1 and 2: SOFT-CORE PROCESSOR DESIGN by Franj
Page 3 and 4: Acknowledgments First, I would like
Page 5 and 6: 5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11 and 12: uilt using techniques proven to be
Page 13 and 14: logic and I/O blocks [11]. Since th
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25: Most instructions take 5 cycles to
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78:
Improvement of UT Nios over Altera
Page 79 and 80:
Improvement of UT Nios over Altera
Page 81 and 82:
Number of Processors LEs (% increas
Page 83 and 84:
pipelined implementation. Control-f
Page 85 and 86:
not mean that, for example, the ins
Page 87 and 88:
There are many paths in each group,
Page 89 and 90:
FPGA design flow is a random functi
Page 91 and 92:
each be connected to only a single
Page 93 and 94:
• The UT Nios design is analyzed
Page 95 and 96:
[13] C. Blum and A. Roli, “Metahe
Page 97 and 98:
[36] Microchip Technology, “PIC16
Page 99:
[60] Altera Corporation, “AN 184:
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