Soft-Core Processor Design - CiteSeer

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Total # of Memory Accesses Performed by the CWP Manager 8000 7000 6000 5000 4000 3000 2000 1000 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of Register Windows Available to the Program Figure 5.7 Modelled number of memory accesses vs. the number of the available register windows for the Fibo benchmark number of the available register windows increases from 4 to 5. This is further augmented by the increasing number of memory operations per exception, as shown in Table 5.1. Comparing the results in Figure 5.7 to the results for Fibo in Figure 5.5 shows that the total number of memory operations caused by the register window exceptions is a good indicator of performance of the Fibo benchmark on the SRAM system. The results are slightly different on the ONCHIP system (Figure 5.4), which is expected because the memory latency is lower, so the memory operations have less impact on the overall performance. To verify the proposed model, we calculated the number of memory operations performed by a simple procedure that performs only a single recursive call at each recursion level (except the last level). The Recursive bit count by nibbles algorithm from the Bitcount benchmark is an example of such program. It performs 8 recursive calls to count the number of bits in the 32-bit input data, and therefore causes from 8 to 0 register window exceptions as the number of the available register windows grows from 1 to 9. More precisely, the number of register window exceptions is 8, 4, 2, 2, 1, 1, 1, 1, 0. Multiplying these numbers by the number of the memory operations per register window exception yields the values shown graphically in Figure 5.8. 62
Total # of Memory Accesses Performed by the CWP Manager 900 800 700 600 500 400 300 200 100 0 1 2 3 4 5 6 7 8 9 10 11 12 Number of Register Windows Available to the Program Figure 5.8 Modelled number of memory accesses vs. the number of the available register windows for simple recursive procedure with recursion depth 8 Comparing this graph with the measurement results for the Recursive bit count by nibbles on the SRAM system (Figure 5.5) again shows that the proposed model approximates well the observed performance behaviour. The correlation is not as precise for the ONCHIP system. The measurement results and their analysis demonstrate that performance may vary with number of available register windows in a complex way. However, a common characteristic of all recursive procedures is that they perform better if register windows are not used than when a limited number of registers, lower than the recursion depth, is used. Since the register window size in the SOPC builder can be selected from three sizes (128, 256, and 512), we use the measurement results to compare the performance of the benchmark set on systems with these register sizes to the performance on a system that does not use the register windows. We assume that one register window is reserved for the interrupt handler, and that the GERMS monitor is not running on the system. Since the measurement results were obtained using a system with the GERMS monitor, the data for the full capacity of 512 registers are not available. These values may be approximated by using the values obtained for a system with one less register window, because the performance difference between systems with a large number of register windows 63
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SOFT-CORE PROCESSOR DESIGN by Franj
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Acknowledgments First, I would like
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5.1.2. Development Tools ..........
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Chapter 1 Introduction Since their
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Chapter 2 Background Soft-core proc
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uilt using techniques proven to be
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logic and I/O blocks [11]. Since th
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timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57 and 58: performance of the UT Nios and Alte
Page 59 and 60: 5.2.1. Performance Dependence on th
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67: Recursion Level # of recursive call
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
Page 83 and 84: pipelined implementation. Control-f
Page 85 and 86: not mean that, for example, the ins
Page 87 and 88: There are many paths in each group,
Page 89 and 90: FPGA design flow is a random functi
Page 91 and 92: each be connected to only a single
Page 93 and 94: • The UT Nios design is analyzed
Page 95 and 96: [13] C. Blum and A. Roli, “Metahe
Page 97 and 98: [36] Microchip Technology, “PIC16
Page 99: [60] Altera Corporation, “AN 184:
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