Soft-Core Processor Design - CiteSeer

pipelined implementation. Control-flow instructions are executed in one cycle by flushing the
prefetch unit and issuing a new instruction address on the negative clock edge, while the rest of
the processor logic is synchronized with the positive clock edge. Therefore, the prefetch unit
issues a new read in the cycle in which the control-flow instruction executes. If only on-chip
memory is used, the new instruction is available with one cycle latency. Since most control-flow
instructions have a delay slot behaviour, there is no branch penalty.
The 2-stage pipelined implementation has a very low cycle count compared to the Altera Nios.
However, the Fmax is also lower, resulting in lower overall performance. The Fmax for this
implementation was 25 MHz, compared with over 100 MHz for the 16-bit Altera Nios in the
same system configuration. Aside from the low performance, the main issue with this
implementation was the register file implementation. Since all instructions execute in a single
cycle, the register file has to be read asynchronously. As mentioned in the introduction to Chapter
4, this is a problem because Stratix FPGAs contain only synchronous memory. Several solutions
to the problem were tried, including implementing the register file in logic, controlling the
synchronous memory with an inverted clock as suggested in [17], and implementing only 32
registers in logic and swapping the values between a large register file in memory and the
registers implemented in logic. Since none of these solutions provided a satisfactory performance,
an additional pipeline stage was introduced, resulting in a 3-stage pipelined design.
The 3-stage pipelined processor was similar to the UT Nios design presented in Chapter 4,
with the operand and execute stages implemented as a single stage. The new pipeline stage was
introduced in a way that allowed the register file to be implemented in the synchronous memory.
The introduction of this stage caused the control-flow instructions to commit one stage later,
causing one cycle of branch penalty. Thus, this implementation had a larger cycle count than the
2-stage implementation. However, the 3-stage implementation achieved the Fmax of 61 MHz, and
performance within 10% of the Altera Nios over a small set of programs used for testing.
The 3-stage implementation was the basis for a 4-stage pipelined implementation. Timing
analysis of the last stage of the pipeline showed that significant gains in Fmax could be achieved
by introducing another pipeline stage, the operand stage, which would include all the logic
feeding the inputs of the ALU. If the branch logic could be included in the operand pipeline stage,
there would be no increase in the cycle count due to the additional branch penalties. However,
after the operand pipeline stage was introduced, flushing the prefetch unit on the negative clock
edge became a limiting factor for Fmax. Using the negative edge of the clock for one design
module, and the positive edge for the rest of the design imposes severe limitations on the timing.
In the worst case, if the module is the slowest part of the design, the Fmax is effectively halved.
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