Soft-Core Processor Design - CiteSeer

prefetch program counter (PPC), which enables fetching of instructions from the target address.
The target address for BR and BSR instructions is calculated in the operand stage of the pipeline.
Calculating the target address in the operand stage, as opposed to the execute stage, enables the
update of the PPC to happen earlier in the pipeline. Updating the PPC earlier ensures that the
instructions from the target address are fetched sooner, which results in fewer pipeline stalls.
Updating the PPC even earlier in the pipeline is not feasible, unless some form of speculative
execution is implemented. The control-flow instruction might be preceded by a skip instruction
whose outcome is unknown before the skip reaches the execute stage. Furthermore, JMP and
CALL instructions use a register value to specify the target address. The value of the register
might be written by an instruction preceding the JMP or CALL, and the result is unknown until
that instruction reaches the execute stage. Values from the execute stage are forwarded to the
branch unit in the same cycle they are calculated in, so that branching may start immediately. For
the TRAP instruction, a target address has to be fetched from a vector table entry in memory.
Since the address of the vector table entry is calculated in the execute stage of the pipeline,
branching is performed in the execute stage when the data memory responds with the target
address. Details of the execute stage modules are described in the following sections.
4.1.6. Arithmetic and Logic Unit
Arithmetic and logic unit (ALU) performs computations specified by the arithmetic and logic
instructions, as well as the memory address calculation for memory instructions. The ALU
consists of several subunits, including the addition/subtraction unit, shifter unit, logic unit, and
the ALU multiplexer. All subunits operate in parallel, and the ALU multiplexer selects the result
of one of the subunits, depending on the instruction being executed.
The addition/subtraction unit is implemented using the lpm_add_sub LPM library component.
The output of the addition/subtraction unit is used directly as a data master memory address.
Since memory addresses are always calculated using the addition/subtraction unit, there is no
need to use the output of the multiplexer for the memory address. Bypassing the multiplexer
reduces the delay of the memory address signals. Data to be written to the data memory using
store instructions is forwarded directly from the O/X pipeline register. As mentioned previously
in section 4.1.4, the addition/subtraction unit is also used for 2’s complement (NEG), and
absolute (ABS) operations. The 2’s complement of a number is calculated by subtracting the
number from 0. The same result is used by an ABS instruction if the original number is negative,
while the result is the number itself if it is positive or zero.
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