[48] Altera Corporation, “GNUPro - User's Guide for Altera Nios,” [Online Document], 2000 June, [Cited 2004 February 20], Available HTTP: http://www.altera.com/literature/third-party/nios_gnupro.pdf [49] Red Hat, Inc., “GNUPro Developer Tools,” [Online Document, Cited 2004 February 20], Available HTTP: http://www.redhat.com/software/gnupro [50] Altera Corporation, “Nios Development Kit, Stratix Edition,” [Online Document, Cited 2004 March 2], Available HTTP: http://www.altera.com/products/devkits/altera/kit-nios_1S10.html [51] Altera Corporation, “Nios Development Kit, Cyclone Edition,” [Online Document, Cited 2004 March 3], Available HTTP: http://www.altera.com/products/devkits/altera/kit-nios_1C20.html [52] Altera Corporation, “Nios Development Kit,” [Online Document, Cited 2004 March 3], Available HTTP: http://www.altera.com/products/devkits/altera/kit-nios.html [53] Altera Corporation, “APEX 20K Device Family Architecture,” [Online Document, Cited 2004 March 4], Available HTTP: http://www.altera.com/products/devices/apex/features/apx-architecture.html#esb [54] Altera Corporation, “Single & Dual-Clock FIFO Megafunctions User Guide,” [Online Document], 2003 June, [Cited 2004 March 4], Available HTTP: http://www.altera.com/literature/ug/ug_fifo.pdf [55] S. Subramanian, A Methodology For Mapping Networking Applications To Multiprocessor-FPGA Configurable Computing Systems, Ph.D. Thesis, North Carolina State University, Raleigh, NC, 2003. [56] M. R. Guthaus and J. S. Ringenberg, D. Ernst, T. M. Austin, T. Mudge, R. B. Brown, “MiBench: A Free, Commercially Representative Embedded Benchmark Suite,” In Proc. of the 4 th IEEE Workshop on Workload Characterization, Austin, TX, 2001, pp. 3-14. [57] L. Shannon and P. Chow, “Standardizing the Performance Assessment of Reconfigurable <strong>Processor</strong> Architectures,” [Online Document, Cited 2004 March 11], Available HTTP: http://www.eecg.toronto.edu/~lesley/benchmarks/rates/shannon_rates.ps [58] Altera Corporation, “ByteBlasterMV Parallel Port Download Cable,” [Online Document], 2002 July, [Cited 2004 March 11], Available HTTP: http://www.altera.com/literature/ds/dsbytemv.pdf [59] Altera Corporation, “Nios Development Board Reference Manual, Stratix Edition,” [Online Document], 2003 July, [Cited 2004 March 11], Available HTTP: http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf 92
[60] Altera Corporation, “AN 184: Simultaneous Multi-Mastering with the Avalon Bus,” [Online Document], 2002 April, [Cited 2004 March 12], Available HTTP: http://www.altera.com/literature/an/an184.pdf [61] Altera Corporation, “AN 284: Implementing Interrupt Service Routines in Nios Systems,” [Online Document], 2003 January, [Cited 2004 March 19], Available HTTP: http://www.altera.com/literature/an/an284.pdf [62] P. R. Panda, N. D. Dutt, A. Nicolau, Memory Issues in Embedded Systems-On-Chip: Optimizations and Exploration, Kluwer Academic Publishers: Norwell, MA, 1999. [63] S. D. Brown and Z. G. Vranesic, Fundamentals of Digital Logic with Verilog <strong>Design</strong>, McGraw-Hill: New York, 2003. [64] Synplicity, Inc., “Synplify & Synplify Pro Products Page,” [Online Document, Cited 2004 March 22], Available HTTP: http://www.synplicity.com/products/synplifypro/index.html [65] Altera Corporation, “<strong>Design</strong>ers Using Linux Now Have Access to Altera's SOPC Solutions,” [Online Document], 2001 April, [Cited 2004 March 22], Available HTTP: http://www.altera.com/corporate/news_room/releases/releases_archive/2001/corporate_p artners/pr-microtronix.html 93
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SOFT-CORE PROCESSOR DESIGN by Franj
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Acknowledgments First, I would like
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5.1.2. Development Tools ..........
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Chapter 1 Introduction Since their
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Chapter 2 Background Soft-core proc
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uilt using techniques proven to be
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logic and I/O blocks [11]. Since th
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timing-driven [11]. Although simula
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the HDL coding style. To ensure tha
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3.1. Nios Architecture The Nios ins
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esult of a read operation from thes
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satisfied the instruction that foll
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Most instructions take 5 cycles to
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contents of the register window wil
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needed, the master asserts the flus
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There are several ways in which use
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code) is provided [47]. Both printf
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memory address has to be set in the
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parameters include the general-purp
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Similarly, the control-flow instruc
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the logic resources may be more cri
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simple dual-port mode, which means
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prefetch program counter (PPC), whi
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