Soft-Core Processor Design - CiteSeer

4.1.4. Operand Handler
Various instruction formats in the Nios instruction set use various operand types. While some
instructions use only register file operands, others also use immediate operands of different sizes.
Depending on the instruction type, the immediate operands are formed by sign-extending,
multiplying by a constant, or concatenating the immediate value encoded in the instruction word
to the value in the K register. The immediate operands can be handled properly only after both the
type of the instruction and the value in the K register are known. The value in the K register is set
when the PFX instruction is in the operand stage of the pipeline. The value set by the PFX
instruction becomes available in the cycle in which the instruction following PFX reaches the
operand stage, and is used to form the immediate operands for that instruction.
After the value of the immediate operand has been calculated, the correct operand can be
selected, depending on the type of the instruction. Some instructions use both register operands,
and some use one of the register operands and the immediate value. TRAP instruction uses a base
address of the vector table, which is a constant, and an immediate operand to calculate the address
of the vector table entry.
Pre-calculating and selecting the operands prior to the execute stage simplifies the design of
the ALU. For instance, the BGEN instruction generates a power of 2 specified by the immediate
operand (2 IMM ). BGEN may be implemented in the ALU as a separate operation. However, it can
also be implemented using a shifter if the first operand is the constant 1 and the second operand is
the immediate operand. Similarly, the 2’s complement operation (NEG instruction) may be
performed by subtracting the number to be complemented from 0. The same result may be used
by the ABS instruction calculating the absolute value if the input value is negative. Simplifying
the ALU in this way is important because the ALU is a part of the critical path in UT Nios.
Besides operand handling and setting the K register value, branching is also performed in the
operand pipeline stage.
4.1.5. Branch Unit
The UT Nios branch unit maintains the correct value of the program counter (PC), used to
calculate the return address for CALL, BSR, and TRAP instructions. The return address is offset
by 2 or 4 from the actual PC value, depending on whether or not the control-flow instruction has
the delay slot behaviour. The return address is forwarded to the execute stage through the pipeline
registers, where it is stored in the appropriate register in the register file.
The PC is updated to the new value in a cycle in which a control-flow instruction is in the
operand stage. In the same cycle the new value is forwarded to the prefetch unit to update the
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