Soft-Core Processor Design - CiteSeer

Chapter 4
UT Nios
Architectural research has traditionally been done by using simulators to evaluate the
performance of proposed systems because building a prototype of a processor in an ASIC is
expensive and time consuming. Soft-core processors are fully described in software and
implemented in programmable hardware, and thus easy to modify. This means that architectural
research on soft-core processors can be performed on actual hardware, while the architecture
parameters are changed by modifying the software. The UT Nios soft-core processor was
developed to get insight into this process and to explore the performance of the Nios architecture.
UT Nios was implemented using Verilog HDL. Verilog was chosen over VHDL because of its
increasing popularity, and because it is simpler to use and understand. UT Nios is customizable
through the use of define and defparam Verilog statements. Its design is optimized for
implementation in FPGAs in the Stratix device family. Stratix was chosen because of the high
amount of memory it contains, which makes it suitable for soft-core processor implementation.
Another reason for choosing Stratix is the availability of the Nios Development Kit, Stratix
Edition [50]. Although Altera also provides a Cyclone Edition [51] and an Apex Edition [52] of
the Nios Development Kit, Stratix is a newer device family, which is likely to be used in Nios
systems. While we focus on a single FPGA device family, UT Nios can easily be adapted for use
on any system that supports design entry using Verilog.
The choice of Stratix as a target FPGA device family had great influence on the design of UT
Nios. As mentioned previously in section 2.4, all the memory available in Stratix FPGAs is
synchronous. Therefore, any read from the memory will incur a latency of at least one clock
cycle, because the data address cannot be captured before the rising edge of the clock [25].
Although the use of the synchronous memory increases the throughput in pipelined designs, any
design using memory necessarily has to be pipelined. For instance, the Nios architecture has a
large general-purpose register file. Implementing this file in logic is impractical due to the
register file size. Therefore, the register file has to be implemented in the synchronous memory,
and the design has to be pipelined. The Stratix documentation [17] suggests that asynchronous
mode may be emulated by clocking the memory using an inverted clock signal (with respect to
the clock controlling the rest of the logic). Memory data would then be available after a half of
the clock cycle. However, this imposes tight constraints on the timing of the rest of the logic. A
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