Soft-Core Processor Design - CiteSeer

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Abstract Soft-Core Processor Design Franjo Plavec Master of Applied Science Graduate Department of Electrical and Computer Engineering University of Toronto 2004 Recent advancements in Field Programmable Gate Array (FPGA) technology have resulted in FPGA devices that support the implementation of a complete computer system on a single FPGA chip. A soft-core processor is a central component of such a system. A soft-core processor is a microprocessor defined in software, which can be synthesized in programmable hardware, such as FPGAs. The Nios soft-core processor from Altera Corporation is studied and a Verilog implementation of the Nios soft-core processor has been developed, called UT Nios. The UT Nios is described, its performance dependence on various architectural parameters is investigated and then compared to the original implementation from Altera. Experiments show that the performance of different types of applications varies significantly depending on the architectural parameters. The performance comparison shows that UT Nios achieves performance comparable to the original implementation. Finally, the design methodology, experiences from the design process and issues encountered are discussed. ii
Acknowledgments First, I would like to thank my supervisors Professor Zvonko Vranesic and Professor Stephen Brown for their advice and support throughout the course of this thesis. I am greatly indebted to you both. A special thanks to Professor Vranesic for his suggestion of the topic of the thesis and for all of the hard work with reading the thesis. I also wish to acknowledge the help of Blair Fort in developing several UT Nios modules and for developing a game that revealed many bugs in the design, causing endless frustration. Also, thank you for all the constructive discussions, whether related to the topic of this thesis or not. Thanks to other people who contributed with their suggestions and ideas. Thanks to Valavan for pointing me to the Design Space Explorer. Thanks to everyone who attended the Altera research meetings, soft-processor research meetings, and the FPGA reading group meetings. Thanks to Nathalie for discovering several bugs and for her interesting questions. Thanks to Lesley for sharing her experiences with Xilinx tools. Thanks to all the students, staff and the faculty of the department and the university for making my work and life on campus a pleasant experience. Special thanks to all the folks in the Croatian Student Association with whom I had many great times. Also, thanks to Ivan for being a good roommate during the past year. I thank Professor Sinisa Srbljic for his suggestion to come to Canada and to pursue studies at U of T. I am greatly indebted to you for your support and advice. I also wish to thank Alex Grbic and his family. They have come forward and accepted me as a part of their family when I needed it the most. Special thanks to Tony for driving me home from many late night parties. Also, thanks to Alex for reading the final draft of this thesis. I wish to thank my mother for teaching me patience, and my father (may his soul rest in peace) for teaching me pertinacity. Without you and your continuous support this work would not have been possible. To my uncle and aunt, Franjo and Vera Plavec for their financial and moral support during my studies, as well as for encouraging me to take the extra English classes. Thanks to all of my friends and family for their love and support. Finally, I wish to thank all of my teachers and professors, past and present. Without you I would not even know how to count, let alone to design a processor. The patience and effort of many of you have motivated me in pursuing science. This work has been financially supported by NSERC, CITR and University of Toronto Master’s Fellowship. I acknowledge and thank them for their support, for this work would not be possible without it. iii
Page 1: SOFT-CORE PROCESSOR DESIGN by Franj
Page 5 and 6: 5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11 and 12: uilt using techniques proven to be
Page 13 and 14: logic and I/O blocks [11]. Since th
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
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Chapter 5 Performance This chapter
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• Qsort: uses the well known qsor
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performance of the UT Nios and Alte
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5.2.1. Performance Dependence on th
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Speedup Over Buffer Size 1 1.6 1.4
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underflow and overflow exceptions a
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Slowdown Over 29 Available Register
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Recursion Level # of recursive call
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Total # of Memory Accesses Performe
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System SRAM ONCHIP Size of the Regi
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a fixed access time, since it is no
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Speedup of the Pipeline Optimized f
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Improvement of UT Nios over Altera
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Improvement of UT Nios over Altera
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Number of Processors LEs (% increas
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pipelined implementation. Control-f
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not mean that, for example, the ins
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There are many paths in each group,
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FPGA design flow is a random functi
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each be connected to only a single
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• The UT Nios design is analyzed
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[13] C. Blum and A. Roli, “Metahe
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[36] Microchip Technology, “PIC16
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[60] Altera Corporation, “AN 184:
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