Soft-Core Processor Design - CiteSeer

Chapter 7
Conclusions and Future Work
The capabilities of FPGAs have increased to the level where it is possible to implement a
complete computer system on a single FPGA chip. The main component in such a system is a
soft-core processor. The Nios soft-core processor is intended for implementation in Altera
FPGAs. In this thesis project a Verilog implementation of the Nios architecture has been
developed, called UT Nios. Performance of UT Nios has been investigated and compared to that
of the Altera Nios. Performance analysis has shown that, although the Altera and UT Nios
implementations are quite different, their performance is similar. Design analysis has shown that
although there is little room for improvement in the current UT Nios organization, there is a lot of
room for experimenting with different processor organizations and architectural parameters.
The thesis offers the following contributions:
• UT Nios implementation of the Nios architecture is described. The incremental design
methodology used in the UT Nios design is described. This methodology resulted in
an unconventional implementation with the performance comparable to the original
implementation from Altera.
• UT Nios benchmark set suitable for evaluation of the soft-core processor based
systems is presented. The benchmark set was selected among the existing benchmarks
and supplemented with benchmarks suitable for performance analysis of the Altera
and UT Nios. All benchmarks were adapted for use on the Nios based systems.
• A detailed analysis of the UT Nios performance and a comparison with the Altera
Nios was performed and the results are presented. The results show that the
application performance varies significantly with various architectural parameters. A
single architectural parameter that influences performance the most is the size of the
general-purpose register file. The results indicate that many applications perform
worse on the system with the windowed register file of small size than on the same
system that does not use register windows capabilities, but uses only a single register
window. The performance comparison of the UT and Altera Nios shows that both
implementations achieve similar performance.
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