Soft-Core Processor Design - CiteSeer

contents of the register window will be restored from the memory. Interrupt handler routines use
the TRET instruction with register %o7 as an argument to return the control to the interrupted
program. Before returning control, the TRET instruction also restores the STATUS register from
the ISTATUS register. If the IE bit was set prior to the occurrence of the interrupt, then restoring
the STATUS register effectively re-enables interrupts, since the STATUS register was saved
before the interrupts were disabled.
Software interrupts are processed regardless of the values of IE and IPRI fields in the status
register. The return address for the software interrupt is the address of the instruction immediately
following the TRAP, since the TRAP instruction does not have the delay slot behaviour. Software
interrupts are in other respects handled as described above. Interrupt number 0 is a non-maskable
interrupt, and its behaviour is not dependent on IE or IPRI fields. It does not use the vector table
entry to determine the interrupt handler address. It is used by the Nios on-chip instrumentation
(OCI) debug module, which is an IP core designed by First Silicon Solutions (FS2) Inc [39]. The
OCI debug module enables advanced debugging by connecting directly to the signals internal to
the Altera Nios CPU [23].
Exceptions do not occur if an unused OP code is issued. An unused OP code is treated as a
NOP by the Altera Nios [40]. Issuing the MUL instruction on a 32-bit Altera Nios that does not
implement the MUL instruction in hardware does not cause an exception, and the result is
undefined [37]. Similarly, the result of the PFXIO operation immediately before any instruction
other than LD or LDP is undefined [23]. Available documentation does not specify the effect of
issuing other optional instructions (e.g. RLC and RRC) when there is no appropriate support in
hardware.
Interrupts are not accepted when the instruction in the branch delay slot is executed because
that would require saving two return addresses: the branch target address and the delay slot
address. Although this behaviour is not specified in the documentation, it follows directly from
[41]. To save logic resources on the FPGA chip, interrupt handling can optionally be turned off if
it is not required by the particular application.
In this section we described the main features of the Altera Nios soft-core processor
architecture. The processor is connected to other system components by using the Avalon bus
[25]. The main characteristics of the Avalon bus are presented in the next section.
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