Soft-Core Processor Design - CiteSeer

Speedup Over Buffer Size 1
1.6
1.4
1.2
1
0.8
0.6
0.4
0.2
0
1 bit/loop
because this benchmark does not experience any stalls if the prefetch unit always has the next
instruction ready. However, with the unit buffer size, the prefetch unit can only issue two reads in
three cycles, because the FIFO buffer has only one register to store the instruction coming from
the memory, while the other one is forwarded to the decode stage immediately. Two instruction
fetches per three clock cycles correspond to the performance improvement of 3/2 when
instructions are fetched continuously, which is the case when the FIFO buffer of size two is used.
This value explains the speedup of the Pipeline benchmark in Figure 5.2. Further increases in the
FIFO buffer size do not influence the performance because the benchmark does not include
memory operations.
Size = 2 Size = 3 Size = 4 Size = 15
Recursive by
nibbles
Non-recursive by
nibbles
Non-recursive by
bytes
Shift and count
CRC32
Figure 5.3 Performance of the application benchmarks vs. the FIFO buffer size
on the SRAM system
The Stringsearch benchmark suffers significant performance penalty when a buffer size of 15
is used over the unit buffer size. The performance of Stringsearch on a system with the FIFO
buffer size 15 was analyzed using ModelSim. We determined that the Stringsearch benchmark
contains store instructions that take as long as 16 cycles to commit. These instructions are targets
of the branches in the program. When a branch commits, the prefetch FIFO buffer is flushed, and
instructions from the target address are fetched. When the store instruction reaches the execute
pipeline stage and issues a write request, the request is not handled before the prefetch unit lowers
55
Dijkstra Large
Game of Life
Patricia
Qsort Large
SHA
Stringsearch