Soft-Core Processor Design - CiteSeer

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5.1.3. System Configuration Two system configurations were used for most performance measurements presented in this chapter: ONCHIP and SRAM. The ONCHIP system configuration consists of the following components: • Altera or UT Nios with varying parameters • 2 Kbytes of 32-bit on-chip memory running GERMS monitor (BOOT memory) • 30 Kbytes of 32-bit on-chip memory used for the program, the data, and the interrupt vector table (PROGRAM memory) • UART peripheral with default settings • Timer peripheral with default settings The Nios data master connects to both memories and both peripherals. The instruction master connects to both memories. All arbitration priorities are set to 1 by default, unless otherwise stated. The SRAM system configuration consists of the following components: • Altera or UT Nios with varying parameters • 16 Kbytes of 32-bit on-chip memory running GERMS monitor (BOOT memory) • 1 MB of 32-bit off-chip SRAM used for the program, the data, and the interrupt vector table (PROGRAM memory) • Avalon tri-state bridge with default settings • UART peripheral with default settings • Timer peripheral with default settings The Nios data master connects to the on-chip memory, tri-state bridge, and all peripherals. The instruction master connects to the on-chip memory and the tri-state bridge. The tri-state bridge connects to the off-chip SRAM. All arbitration priorities are set to 1 by default, unless otherwise stated. 5.2. UT Nios Performance As described in the previous chapter, there are several customizable parameters in the UT Nios implementation. In the following sections we present how the performance depends on two parameters that, according to our measurements, influence performance the most: the prefetch FIFO buffer size and the general-purpose register file size. We also discuss the effect of other parameters on the performance of UT Nios. 52
5.2.1. Performance Dependence on the Prefetch FIFO Buffer Size The prefetch FIFO buffer size determines how many instructions may be fetched before they are actually needed. We ran the benchmarks using both the ONCHIP and the SRAM system configurations with the UT Nios processor. The processor was configured to use the general- purpose register file with 512 registers. The size of the FIFO buffer was varied from 1 to 4. We also measured the performance with a buffer size of 15, to simulate the buffer of infinite size. Figures 5.1 through 5.3 show how the performance of the benchmark programs depends on the FIFO buffer size. All values are relative to the unit FIFO buffer size. Each of the algorithms in the Bitcount benchmark is presented separately, because the behaviour of the algorithms with respect to the FIFO buffer size is different. For the benchmarks with two datasets, we present the results of the large dataset only, since both datasets show the same performance trends with respect to the FIFO buffer size. For the ONCHIP system, only Bitcount, toy and test benchmark results are presented, since only these benchmarks fit in the small on-chip memory. Speedup Over Buffer Size 1 1.02 1 0.98 0.96 0.94 0.92 0.9 0.88 0.86 0.84 0.82 Fibo Size = 2 Size = 3 Size = 4 Size = 15 Multiply QsortInt Loops Memory Pipeline 53 Pipeline-Memory (BOOT) Pipeline-Memory (PROGRAM) 1 bit/loop Recursive by nibbles Non-recursive by nibbles Figure 5.1 Performance vs. the FIFO buffer size on the ONCHIP system Non-recursive by bytes Shift and count
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SOFT-CORE PROCESSOR DESIGN by Franj
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Acknowledgments First, I would like
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5.1.2. Development Tools ..........
Page 7 and 8: Chapter 1 Introduction Since their
Page 9 and 10: Chapter 2 Background Soft-core proc
Page 11 and 12: uilt using techniques proven to be
Page 13 and 14: logic and I/O blocks [11]. Since th
Page 15 and 16: timing-driven [11]. Although simula
Page 17 and 18: the HDL coding style. To ensure tha
Page 19 and 20: 3.1. Nios Architecture The Nios ins
Page 21 and 22: esult of a read operation from thes
Page 23 and 24: satisfied the instruction that foll
Page 25 and 26: Most instructions take 5 cycles to
Page 27 and 28: contents of the register window wil
Page 29 and 30: needed, the master asserts the flus
Page 31 and 32: There are several ways in which use
Page 33 and 34: code) is provided [47]. Both printf
Page 35 and 36: memory address has to be set in the
Page 37 and 38: parameters include the general-purp
Page 39 and 40: Similarly, the control-flow instruc
Page 41 and 42: the logic resources may be more cri
Page 43 and 44: simple dual-port mode, which means
Page 45 and 46: prefetch program counter (PPC), whi
Page 47 and 48: There are two ways to resolve data
Page 49 and 50: individual bits (e.g. flags), and g
Page 51 and 52: LOAD state, except that a memory wr
Page 53 and 54: Chapter 5 Performance This chapter
Page 55 and 56: • Qsort: uses the well known qsor
Page 57: performance of the UT Nios and Alte
Page 61 and 62: Speedup Over Buffer Size 1 1.6 1.4
Page 63 and 64: underflow and overflow exceptions a
Page 65 and 66: Slowdown Over 29 Available Register
Page 67 and 68: Recursion Level # of recursive call
Page 69 and 70: Total # of Memory Accesses Performe
Page 71 and 72: System SRAM ONCHIP Size of the Regi
Page 73 and 74: a fixed access time, since it is no
Page 75 and 76: Speedup of the Pipeline Optimized f
Page 77 and 78: Improvement of UT Nios over Altera
Page 79 and 80: Improvement of UT Nios over Altera
Page 81 and 82: Number of Processors LEs (% increas
Page 83 and 84: pipelined implementation. Control-f
Page 85 and 86: not mean that, for example, the ins
Page 87 and 88: There are many paths in each group,
Page 89 and 90: FPGA design flow is a random functi
Page 91 and 92: each be connected to only a single
Page 93 and 94: • The UT Nios design is analyzed
Page 95 and 96: [13] C. Blum and A. Roli, “Metahe
Page 97 and 98: [36] Microchip Technology, “PIC16
Page 99: [60] Altera Corporation, “AN 184:
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