Agilent 34970A/34972A Data Acquisition / Switch Unit

Chapter 5 Theory of Operation
Memory
Memory
Unless otherwise noted, components in this discussion are located on the
A1 circuit assembly (34970-66501).
The main controller, U205, uses 512 Kbytes of ROM and 544 Kbytes of
RAM. ASIC U209 provides the memory mapping that allows access to
this large memory space. The memory map as seen by the main
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controller is as follows:
Address
0100H thru 1FBFH
0100H thru 1FBFH
1FC0H thru 1FDFH
2000H thru 5FFFH
6000H thru 7FFFH
6000H thru 7FFFH
8000H thru FFFFH
Maps to
00100H thru 01FBFH in RAM for data fetches
00100H thru 01FBFH in ROM for instrument fetches
registers in U209
02000H thru 05FFFH in ROM
06000H thru 07FFFH in RAM for data fetches
06000H thru 07FFFH in ROM for instrument fetches
any selected 32 Kbyte page of ROM or RAM
The memory is organized with a 16-bit data bus (AD(15:0)) and a 19-bit
address bus (MA(19:1)). The memory address is produced by U209
latching the address present on AD(15:0) when U205 asserts ALE_FLT.
Reads of memory are always 16-bits wide (there is a single RD_N signal).
Writes, however, can be byte-wide and therefore U209 produces both a
high-byte write strobe, MWRH_N, and a low-byte write strobe,
MWRL_N. These write signals are based on the latched 0-bit of the
address and the BHE_N signal produced by the main controller, U205.
The ROM memory consists of a single, 256Kx16 device, U401. The RAM
memory consists of five devices: U402, U403, U404, U405, and U410. A
uniform, 256Kx16, memory block is formed by the four 128Kx8 devices,
U402 through U405. A separate, 32Kx8 block is formed by U410 and is
available through special programming of U209.
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