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124 P. Petoumenos et al. comparable in the number of instructions to the maximum IQ size. MLP information is associated with superpaths and is used to override resizing decisions that might harm the MLP of the superpath. In absence of misses and MLP, resizing of the IQ is performed using already existing techniques. Our results show that we can manage the IQ, considerably better than in prior approaches yielding consistently better EDP over the base case. At the same time, we can push the resizing of the IQ much more aggressively (to achieve better energy savings) knowing that our safety-net mechanism protects the MLP of the program and will not inordinately harm performance. Acknowledgments. This work is supported by the EU FP6 Integrated Project - Future and Emerging Technologies, Scalable computer ARCitecture (SARC) Contract No. 27648, and the EU FP6 HiPEAC Network of Excellence IST-004408. The equipment used for this work is a donation by Intel Corporation under Intel Research Equipment Grant #15842. References [1] Buyuktosunoglu, A., Albonesi, D., Schuster, S., Brooks, D., Bose, P., Cook, P.: A Circuit Level Implementation of an Adaptive Issue Queue for Power–Aware Microprocessors. In: Proc. of Great Lakes Symposium on VLSI Design (2001) [2] Folegnani, D., González, A.: Energy-effective issue logic. In: Proc. of the International Symposium on Computer Architecture (2001) [3] Kucuk, G., Ghose, K., Ponomarev, D.V., Kogge, P.M.: Energy-Efficient Instruction Dispatch Buffer Design for Superscalar Processors. In: Proc. of the International Symposium on Low Power Electronics and Design (2001) [4] Eyerman, S., Eeckhout, L.: A Memory-Level Parallelism Aware Fetch Policy for SMT Processors. In: Proc. of the International Symposium on High Performance Computer Architecture (2007) [5] Glew, A.: MLP yes! ILP no! In: ASPLOS Wild and Crazy Ideas Session 1998 (1998) [6] Karkhanis, T.S., Smith, J.E.: A first-order uperscalar processor model. In: Proc. of the International Symposium on Computer Architecture (2004) [7] Chou, Y., Fahs, B., Abraham, S.: Microarchitecture optimizations for exploiting memorylevel parallelism. In: Proc. of the International Symposium on Computer Architecture (2004) [8] Qureshi, M.K., Lynch, D.N., Mutlu, O., Patt, Y.N.: A Case for MLP-Aware Cache Replacement. In: Proc. of the International Symposium on Computer Architecture (2006) [9] Sohi, G.S., Vajapeyam, S.: Instruction Issue Logic for High-Performance, Interruptable Pipelined Processors. In: Proc. of the International Symposium on Computer Architecture (1987) [10] Ghose, K., Kamble, M.B.: Reducing Power in Superscalar Processor Caches using Subbanking, Multiple Line Buffers, and Bit Line Segmentation. In: Proc. of the International Symposium on Low Power Electronics and Design (1999) [11] Ponomarev, D., Kucuk, G., Ghose, K.: Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency. IEEE Transactions on Computers (2006) [12] Iyer, A., Marculescu, D.: Power aware microarchitecture resource scaling. Design, Automation and Test in Europe (2001)
MLP-Aware Instruction Queue Resizing: The Key to Power-Efficient Performance 125 [13] Rotenberg, E., Smith, J., Bennett, S.: Trace Cache: a Low Latency Approach to High Bandwidth Instruction Fetching. In: Proc. of the International Symposium on Microarchitecture (1996) [14] Tarjan, D., Thoziyoor, S., Jouppi, N.P.: CACTI 4.0. Hewlett-Packard Laboratories Technical Report #HPL-2006-86 (2006) [15] Brooks, D.M., Tiwari, V., Martonosi, M.: Wattch: A framework for architectural-level power analysis and optimizations. In: Proc. of the International Symposium Computer Architecture (2000) [16] Gonzalez, R., Horowitz, M.: Energy Dissipation in General Purpose Microprocessors. IEEE J. Solid-State Circuits (1996) [17] Zyuban, V., Brooks, D., Srinivasan, V., Gschwind, M., Bose, P., Strenski, P.N., Emma, P.G.: Integrated Analysis of Power and Performance of Pipelined Microprocessors. IEEE Transactions on Computers (2004)
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Lecture Notes in Computer Science 5
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Volume Editors Christian Müller-Sc
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General Chair Organization Christia
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Organization IX Hartmut Schmeck Kar
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Keynote Table of Contents HyVM - Hy
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Table of Contents XIII JetBench:AnO
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How to Enhance a Superscalar Proces
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4 J. Mische et al. The Real-time Vi
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6 J. Mische et al. 4.1 Instruction
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8 J. Mische et al. Additionally the
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10 J. Mische et al. % of unused pip
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12 J. Mische et al. % of cycles spe
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14 J. Mische et al. 16. Lickly, B.,
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16 G. Aşılıoğlu, E.M. Kaya, and
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26 T.B. Preußer, P. Reichel, and R
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38 P. Bellasi, W. Fornaciari, and D
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50 J. Zeppenfeld and A. Herkersdorf
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62 B. Jakimovski, B. Meyer, and E.
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Effect of the Degree of Neighborhoo
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176 T. Abdullah et al. A zone based
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178 T. Abdullah et al. A consumer/p
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180 T. Abdullah et al. Messages 140
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184 T. Abdullah et al. % Matchmakin
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200 R. Plyaskin and A. Herkersdorf
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226 F. Nowak and R. Buchty Fig. 3.
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228 F. Nowak and R. Buchty Table 2.
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Optimizing Stencil Application on M
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236 F. Xudong et al. compared to th
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238 F. Xudong et al. stencil comput
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240 F. Xudong et al. threads in the
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242 F. Xudong et al. Speedup 14 12
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244 F. Xudong et al. 5 Related Work
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Abdullah, Tariq 174 Alima, Luc Onan
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