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244 F. Xudong et al.
5 Related Work
With the popular adoption of GPUs in scientific computing, much research has
recently been performed in optimizing GPU applications using general programming
languages such as Brook+ and CUDA.
Ryoo et al. proposed optimization principles for efficient mapping of computation
to graphics hardware [11]. Their main concern was using massive multithreading
to exploit the rich stream core resource and hide memory fetch latency.
Jang et al. presented an optimization methodology that utilizes architectural information
to accelerate programs on AMD GPUs [12]. They exploited optimizations
by defining optimization spaces. Their work demonstrated many AMD
GPU details. Wang et al. presented GPU implementation of Mgrid using CUDA
in the single precision floating point version [13]. They exploited data locality
in 3-level memory hierarchies and tuned thread granularity thus reducing the
pressure on the off-chip memory bandwidth. Due to architecture deviation, their
optimization strategies can not directly applied using Brook+ on AMD GPUs.
In our work, we choose Mgrid since its stencil computations provide rich
opportunity for exploiting on-chip parallelism and hiding memory accessing latencies.
Li et al. proposed a compiler framework for automatic tiling of iterative
stencil loops to improve the cache reuse [14]. Krishnamoorthy et al. developed
an approach for automatic parallelization of stencil codes, explicitly addressing
the issue of load-balanced execution of tiles caused by loop skewing in the time
dimension [4]. They focused on improving cache locality of the CPU.
6 Conclusions and Future Work
In this paper, we implemented and optimized a real benchmark application Mgrid
on AMD Radeon HD4870 GPU, and achieved very good experimental results.
Though our implementation and optimizations are based on Mgrid, theoptimization
strategies can be use to improve any stencil computations. In the future, we
would like to determine thread granularity automatically to simplify the application
optimization on the GPU; and we would also consider exploring the GPU
application performance at the intermediate language (IL) level. To fully exploit
the CPU and GPU heterogeneous platform, we would try to automatically
distribute tasks between the two computing resources.
References
1. AMD.: Ati stream computing user guide v1.4beta (2009),
http://developer.amd.com/gpu_assets/Stream_Computing_User_Guide.pdf
2. NVIDIA.: Compute unified device architecture programming guide v2.1beta
(2009),
http://developer.download.nvidia.com/compute/cuda/
1 0/NVIDIA CUDA Programming Guide 1.0.pdf