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Architecture of Computing Systems (Lecture Notes in Computer ...

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136 M. Kayaalp et al.<br />

The results <strong>of</strong> our study shows an upper bound for the benefits that can be achieved<br />

by us<strong>in</strong>g the dependency check<strong>in</strong>g logic <strong>of</strong> the rename stage s<strong>in</strong>ce it is assumed that<br />

each and every <strong>in</strong>struction uses the dest<strong>in</strong>ation and source tags. In reality, many <strong>in</strong>structions<br />

don’t use some or all <strong>of</strong> these tag fields and this observation was used for<br />

different purposes by many researchers [3][15][20]. By us<strong>in</strong>g the unused space <strong>in</strong>side<br />

the <strong>in</strong>struction slots, it is possible to use the on-chip comparators for detect<strong>in</strong>g more<br />

errors on the register tags. The <strong>in</strong>vestigation <strong>of</strong> how to use the unused register tag<br />

space for s<strong>of</strong>t error detection is left for future work.<br />

Acknowledgments<br />

This work was supported <strong>in</strong> part by the Scientific and Technological Research Council<br />

<strong>of</strong> Turkey (TUBITAK) through the research grants 107E043 and 109E43, by the<br />

European Network <strong>of</strong> Excellence on High Performance and Embedded <strong>Architecture</strong><br />

and Compilation (HiPEAC) through the “Reliable Embedded Processors” research<br />

cluster and by the European Union (FEDER funds) under contract TIN2007-60625.<br />

References<br />

1. Baumann, R.: S<strong>of</strong>t Errors <strong>in</strong> Advanced <strong>Computer</strong> <strong>Systems</strong>. IEEE Design & Test <strong>of</strong> <strong>Computer</strong>s<br />

22(3), 258–266 (2005)<br />

2. Erg<strong>in</strong>, O., Unsal, O., Vera, X., González, A.: Exploit<strong>in</strong>g Narrow Values for S<strong>of</strong>t Error Tolerance.<br />

IEEE <strong>Computer</strong> <strong>Architecture</strong> Letters (CAL) 5, 12–15 (2006)<br />

3. Erg<strong>in</strong>, O., Yalc<strong>in</strong>, G., Unsal, O., Valero, M.: Exploit<strong>in</strong>g the Dependency Check<strong>in</strong>g Logic<br />

<strong>of</strong> the Rename Stage for S<strong>of</strong>t Error Detection. In: 1st Workshop on Design for Reliability<br />

(DFR 2009) (January 2009)<br />

4. Ernst, D., Aust<strong>in</strong>, T.: Efficient Dynamic Schedul<strong>in</strong>g Through Tag Elim<strong>in</strong>ation. In: ISCA,<br />

vol. 30, pp. 37–46 (2002)<br />

5. Gochman, S., Mendelson, A., Naveh, A., Rotem, E.: Introduction to Intel Core Duo Processor<br />

<strong>Architecture</strong>. Intel Technology Journal 10(2) (May 2006)<br />

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Journal 5(1) (February 2001)<br />

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for transient fault detect<strong>in</strong>g superscalar microarchitectures. In: Srikanthan, T., Xue, J.,<br />

Chang, C.-H. (eds.) ACSAC 2005. LNCS, vol. 3740, pp. 200–214. Spr<strong>in</strong>ger, Heidelberg<br />

(2005)<br />

8. Kessler, R.E.: The Alpha 21264 Microprocessor. IEEE Micro 19(2), 24–36 (1999)<br />

9. Moshovos, A.: Power Aware Register Renam<strong>in</strong>g, <strong>Computer</strong> Eng<strong>in</strong>eer<strong>in</strong>g Group Technical<br />

Report 01-08-2, University <strong>of</strong> Toronto (2002)<br />

10. Mukherjee, S.S., et al.: A Systematic Methodology to Compute the Architectural Vulnerability<br />

Factors for a High-Performance Microprocessor. In: MICRO, pp. 29–40 (2003)<br />

11. Mukherjee, S.S., et al.: Detailed Design and Evaluation <strong>of</strong> Redundant Multithread<strong>in</strong>g Alternatives.<br />

In: ISCA, vol. 30(2), pp. 99–110 (2002)<br />

12. Phelan, R.: Address<strong>in</strong>g S<strong>of</strong>t Errors <strong>in</strong> ARM Core-based Designs, White Paper, ARM<br />

(December 2003)<br />

13. Re<strong>in</strong>hardt, S.K., Mukherjee, S.S.: Transient Fault Detection via Simultaneous Multithread<strong>in</strong>g.<br />

In: ISCA, vol. 28(2), pp. 25–36 (2000)

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